mirror of https://github.com/YosysHQ/yosys.git
kernel/mem: Add prepare_wr_merge helper.
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@ -786,3 +786,23 @@ void Mem::emulate_priority(int idx1, int idx2)
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}
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port2.priority_mask[idx1] = false;
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}
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void Mem::prepare_wr_merge(int idx1, int idx2) {
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log_assert(idx1 < idx2);
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auto &port1 = wr_ports[idx1];
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auto &port2 = wr_ports[idx2];
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// If port 2 has priority over a port before port 1, make port 1 have priority too.
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for (int i = 0; i < idx1; i++)
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if (port2.priority_mask[i])
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port1.priority_mask[i] = true;
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// If port 2 has priority over a port after port 1, emulate it.
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for (int i = idx1 + 1; i < idx2; i++)
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if (port2.priority_mask[i])
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emulate_priority(i, idx2);
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// If some port had priority over port 2, make it have priority over the merged port too.
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for (int i = idx2 + 1; i < GetSize(wr_ports); i++) {
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auto &oport = wr_ports[i];
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if (oport.priority_mask[idx2])
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oport.priority_mask[idx1] = true;
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}
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}
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@ -84,6 +84,13 @@ struct Mem {
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// from the priority mask.
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void emulate_priority(int idx1, int idx2);
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// Prepares for merging write port idx2 into idx1 (where idx1 < idx2).
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// Specifically, takes care of priority masks: any priority relations
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// that idx2 had are replicated onto idx1, unless they conflict with
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// priorities already present on idx1, in which case emulate_priority
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// is called.
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void prepare_wr_merge(int idx1, int idx2);
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Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}
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};
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