mirror of https://github.com/YosysHQ/yosys.git
Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten.
Add back statement that inserts nodes in order in opt_expr.cc.
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@ -174,11 +174,7 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
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void edge(T left, T right) { edge(node(left), node(right)); }
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bool has_edges(const T &node)
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{
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auto it = node_to_index.find(node);
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return it == node_to_index.end() || !edges[it->second].empty();
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}
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bool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }
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bool sort()
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{
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@ -192,8 +188,6 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
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std::vector<bool> marked_cells(edges.size(), false);
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std::vector<bool> active_cells(edges.size(), false);
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std::vector<int> active_stack;
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marked_cells.reserve(edges.size());
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sorted.reserve(edges.size());
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for (const auto &it : node_to_index)
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@ -582,7 +582,7 @@ struct GliftPass : public Pass {
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for (auto cell : module->selected_cells()) {
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RTLIL::Module *tpl = design->module(cell->type);
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if (tpl != nullptr) {
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if (!topo_modules.has_edges(tpl))
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if (!topo_modules.has_node(tpl))
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worklist.push_back(tpl);
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topo_modules.edge(tpl, module);
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non_top_modules.insert(cell->type);
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@ -424,6 +424,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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for (auto &bit : sig)
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outbit_to_cell[bit].insert(cell);
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}
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cells.node(cell);
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}
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// Build the graph for the topological sort.
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@ -312,7 +312,7 @@ struct FlattenPass : public Pass {
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for (auto cell : module->selected_cells()) {
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RTLIL::Module *tpl = design->module(cell->type);
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if (tpl != nullptr) {
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if (!topo_modules.has_edges(tpl))
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if (!topo_modules.has_node(tpl))
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worklist.insert(tpl);
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topo_modules.edge(tpl, module);
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}
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