mirror of https://github.com/YosysHQ/yosys.git
fmt: function name typo
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1a222cb163
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@ -214,7 +214,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
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cell->setPort(ID(ARGS), args);
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}
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static size_t compute_requried_decimal_places(size_t size, bool signed_)
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static size_t compute_required_decimal_places(size_t size, bool signed_)
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{
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BigUnsigned max;
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if (!signed_)
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@ -234,7 +234,7 @@ static size_t compute_requried_decimal_places(size_t size, bool signed_)
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static void apply_verilog_automatic_sizing(FmtPart &part)
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{
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if (part.base == 10) {
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size_t places = compute_requried_decimal_places(part.sig.size(), part.signed_);
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size_t places = compute_required_decimal_places(part.sig.size(), part.signed_);
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part.padding = ' ';
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part.width = std::max(part.width, places);
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} else {
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