mirror of https://github.com/YosysHQ/yosys.git
Support import of $future_ff
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9c255c98b1
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27ac912709
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@ -1142,6 +1142,11 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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module->connect(operatorOutput(inst),module->OriginalTag(new_verific_id(inst), tag, operatorInput(inst)));
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return true;
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}
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if (inst->Type() == OPER_YOSYSHQ_FUTURE_FF)
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{
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module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst)));
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return true;
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}
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#undef IN
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#undef IN1
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@ -106,6 +106,7 @@ struct CellTypes
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setup_type(ID($get_tag), {ID::A}, {ID::Y});
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setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
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setup_type(ID($original_tag), {ID::A}, {ID::Y});
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setup_type(ID($future_ff), {ID::A}, {ID::Y});
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}
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void setup_internals_eval()
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@ -1855,6 +1855,13 @@ namespace {
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check_expected();
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return;
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}
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if (cell->type.in(ID($future_ff))) {
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param(ID::WIDTH);
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port(ID::A, param(ID::WIDTH));
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port(ID::Y, param(ID::WIDTH));
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check_expected();
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return;
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}
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error(__LINE__);
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}
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};
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@ -3323,6 +3330,17 @@ RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::strin
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return sig;
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}
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RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src)
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{
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RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
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Cell *cell = addCell(name, ID($future_ff));
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cell->parameters[ID::WIDTH] = sig_e.size();
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cell->setPort(ID::A, sig_e);
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cell->setPort(ID::Y, sig);
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cell->set_src_attribute(src);
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return sig;
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}
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RTLIL::Wire::Wire()
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{
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static unsigned int hashidx_count = 123456789;
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@ -1469,6 +1469,7 @@ public:
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RTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const std::string &src = "");
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RTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
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RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const std::string &src = "");
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RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = "");
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#ifdef WITH_PYTHON
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static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
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@ -2728,3 +2728,16 @@ assign Y = A;
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endmodule
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// --------------------------------------------------------
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module \$future_ff (A, Y);
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parameter WIDTH = 0;
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input [WIDTH-1:0] A;
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output [WIDTH-1:0] Y;
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assign Y = A;
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endmodule
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// --------------------------------------------------------
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