Support import of $future_ff

This commit is contained in:
Miodrag Milanovic 2023-08-24 11:55:30 +02:00 committed by Jannis Harder
parent 9c255c98b1
commit 27ac912709
5 changed files with 38 additions and 0 deletions

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@ -1142,6 +1142,11 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
module->connect(operatorOutput(inst),module->OriginalTag(new_verific_id(inst), tag, operatorInput(inst)));
return true;
}
if (inst->Type() == OPER_YOSYSHQ_FUTURE_FF)
{
module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst)));
return true;
}
#undef IN
#undef IN1

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@ -106,6 +106,7 @@ struct CellTypes
setup_type(ID($get_tag), {ID::A}, {ID::Y});
setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
setup_type(ID($original_tag), {ID::A}, {ID::Y});
setup_type(ID($future_ff), {ID::A}, {ID::Y});
}
void setup_internals_eval()

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@ -1855,6 +1855,13 @@ namespace {
check_expected();
return;
}
if (cell->type.in(ID($future_ff))) {
param(ID::WIDTH);
port(ID::A, param(ID::WIDTH));
port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
error(__LINE__);
}
};
@ -3323,6 +3330,17 @@ RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::strin
return sig;
}
RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
Cell *cell = addCell(name, ID($future_ff));
cell->parameters[ID::WIDTH] = sig_e.size();
cell->setPort(ID::A, sig_e);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
}
RTLIL::Wire::Wire()
{
static unsigned int hashidx_count = 123456789;

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@ -1469,6 +1469,7 @@ public:
RTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const std::string &src = "");
RTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const std::string &src = "");
RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = "");
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);

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@ -2728,3 +2728,16 @@ assign Y = A;
endmodule
// --------------------------------------------------------
module \$future_ff (A, Y);
parameter WIDTH = 0;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
assign Y = A;
endmodule
// --------------------------------------------------------