mirror of https://github.com/YosysHQ/yosys.git
New kernel/yw.{h,cc} to support reading Yosys witness files
This contains parsing code as well as generic routines to associate the hierarchical signals paths within a Yosys witness file to a loaded RTLIL design, including support for memories.
This commit is contained in:
Jannis Harder
parent
f6458bab70
commit
1494cfff00
2
Makefile
2
Makefile
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@ -653,7 +653,7 @@ ifneq ($(ABCEXTERNAL),)
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kernel/yosys.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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endif
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endif
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OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o
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OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o
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ifeq ($(ENABLE_ZLIB),1)
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OBJS += kernel/fstdata.o
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endif
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@ -0,0 +1,209 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yw.h"
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#include "libs/json11/json11.hpp"
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USING_YOSYS_NAMESPACE
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// Use the same formatting as witness.py uses
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static const char *pretty_name(IdString id)
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{
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const char *c_str = id.c_str();
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const char *p = c_str;
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if (*p != '\\')
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return c_str;
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p++;
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if (*p == '[') {
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p++;
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while (*p >= '0' && *p <= '9')
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p++;
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if (p[0] != ']' || p[1] != 0)
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return c_str;
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return c_str + 1;
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}
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if (!(*p >= 'a' && *p <= 'z') && !(*p >= 'A' && *p <= 'Z') && *p != '_')
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return c_str;
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p++;
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while ((*p >= '0' && *p <= '9') || (*p >= 'a' && *p <= 'z') || (*p >= 'A' && *p <= 'Z') || *p == '_')
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p++;
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if (*p != 0)
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return c_str;
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return c_str + 1;
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}
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std::string IdPath::str() const
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{
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std::string result;
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for (auto &item : *this) {
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const char *pretty = pretty_name(item);
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if (pretty[0] == '[') {
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result += pretty;
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continue;
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}
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if (!result.empty())
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result += '.';
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result += pretty;
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if (pretty[0] == '\\' || pretty[0] == '$')
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result += ' ';
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}
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return result;
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}
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bool IdPath::get_address(int &addr) const
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{
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if (empty())
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return false;
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auto &last = back();
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if (!last.begins_with("\\["))
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return false;
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if (last == "\\[0]") {
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addr = 0;
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return true;
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}
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char first = last.c_str()[2];
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if (first < '1' || first > '9')
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return false;
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char *endptr;
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addr = std::strtol(last.c_str() + 2, &endptr, 10);
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return endptr[0] == ']' && endptr[1] == 0;
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}
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static std::vector<IdString> get_path(const json11::Json &json)
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{
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std::vector<IdString> result;
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for (auto &path_item : json.array_items()) {
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auto const &path_item_str = path_item.string_value();
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if (path_item_str.empty())
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return {};;
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result.push_back(path_item_str);
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}
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return result;
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}
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ReadWitness::ReadWitness(const std::string &filename) :
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filename(filename)
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{
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std::ifstream f(filename.c_str());
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if (f.fail() || GetSize(filename) == 0)
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log_error("Cannot open file `%s`\n", filename.c_str());
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std::stringstream buf;
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buf << f.rdbuf();
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std::string err;
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json11::Json json = json11::Json::parse(buf.str(), err);
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if (!err.empty())
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log_error("Failed to parse `%s`: %s\n", filename.c_str(), err.c_str());
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std::string format = json["format"].string_value();
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if (format.empty())
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log_error("Failed to parse `%s`: Unknown format\n", filename.c_str());
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if (format != "Yosys Witness Trace")
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log_error("Failed to parse `%s`: Unsupported format `%s`\n", filename.c_str(), format.c_str());
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for (auto &clock_json : json["clocks"].array_items()) {
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Clock clock;
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clock.path = get_path(clock_json["path"]);
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if (clock.path.empty())
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log_error("Failed to parse `%s`: Missing path for clock `%s`\n", filename.c_str(), clock_json.dump().c_str());
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auto edge_str = clock_json["edge"];
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if (edge_str.string_value() == "posedge")
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clock.is_posedge = true;
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else if (edge_str.string_value() == "negedge")
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clock.is_negedge = true;
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else
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log_error("Failed to parse `%s`: Unknown edge type for clock `%s`\n", filename.c_str(), clock_json.dump().c_str());
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if (!clock_json["offset"].is_number())
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log_error("Failed to parse `%s`: Unknown offset for clock `%s`\n", filename.c_str(), clock_json.dump().c_str());
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clock.offset = clock_json["offset"].int_value();
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if (clock.offset < 0)
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log_error("Failed to parse `%s`: Invalid offset for clock `%s`\n", filename.c_str(), clock_json.dump().c_str());
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clocks.push_back(clock);
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}
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int bits_offset = 0;
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for (auto &signal_json : json["signals"].array_items()) {
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Signal signal;
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signal.bits_offset = bits_offset;
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signal.path = get_path(signal_json["path"]);
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if (signal.path.empty())
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log_error("Failed to parse `%s`: Missing path for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
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if (!signal_json["width"].is_number())
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log_error("Failed to parse `%s`: Unknown width for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
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signal.width = signal_json["width"].int_value();
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if (signal.width < 0)
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log_error("Failed to parse `%s`: Invalid width for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
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bits_offset += signal.width;
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if (!signal_json["offset"].is_number())
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log_error("Failed to parse `%s`: Unknown offset for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
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signal.offset = signal_json["offset"].int_value();
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if (signal.offset < 0)
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log_error("Failed to parse `%s`: Invalid offset for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
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signal.init_only = json["init_only"].bool_value();
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signals.push_back(signal);
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}
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for (auto &step_json : json["steps"].array_items()) {
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Step step;
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if (!step_json["bits"].is_string())
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log_error("Failed to parse `%s`: Expected string as bits value for step %d\n", filename.c_str(), GetSize(steps));
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step.bits = step_json["bits"].string_value();
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for (char c : step.bits) {
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if (c != '0' && c != '1' && c != 'x' && c != '?')
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log_error("Failed to parse `%s`: Invalid bit '%c' value for step %d\n", filename.c_str(), c, GetSize(steps));
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}
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steps.push_back(step);
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}
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}
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RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const
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{
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log_assert(t >= 0 && t < GetSize(steps));
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const std::string &bits = steps[t].bits;
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RTLIL::Const result(State::Sa, width);
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result.bits.reserve(width);
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int read_begin = GetSize(bits) - 1 - bits_offset;
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int read_end = max(-1, read_begin - width);
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min(width, GetSize(bits) - bits_offset);
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for (int i = read_begin, j = 0; i > read_end; i--, j++) {
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RTLIL::State bit = State::Sa;
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switch (bits[i]) {
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case '0': bit = State::S0; break;
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case '1': bit = State::S1; break;
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case 'x': bit = State::Sx; break;
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case '?': bit = State::Sa; break;
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default:
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log_abort();
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}
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result.bits[j] = bit;
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}
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return result;
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}
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@ -0,0 +1,170 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef YW_H
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#define YW_H
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#include "kernel/yosys.h"
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#include "kernel/mem.h"
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YOSYS_NAMESPACE_BEGIN
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struct IdPath : public std::vector<RTLIL::IdString>
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{
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template<typename... T>
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IdPath(T&&... args) : std::vector<RTLIL::IdString>(std::forward<T>(args)...) { }
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IdPath prefix() const { return {begin(), end() - !empty()}; }
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std::string str() const;
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bool has_address() const { int tmp; return get_address(tmp); };
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bool get_address(int &addr) const;
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int hash() const { return hashlib::hash_ops<std::vector<RTLIL::IdString>>::hash(*this); }
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};
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struct WitnessHierarchyItem {
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RTLIL::Module *module;
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RTLIL::Wire *wire = nullptr;
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RTLIL::Cell *cell = nullptr;
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Mem *mem = nullptr;
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WitnessHierarchyItem(RTLIL::Module *module, RTLIL::Wire *wire) : module(module), wire(wire) {}
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WitnessHierarchyItem(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) {}
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WitnessHierarchyItem(RTLIL::Module *module, Mem *mem) : module(module), mem(mem) {}
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};
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template<typename D, typename T>
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void witness_hierarchy(RTLIL::Module *module, D data, T callback);
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struct ReadWitness
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{
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struct Clock {
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IdPath path;
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int offset;
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bool is_posedge;
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bool is_negedge;
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};
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struct Signal {
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IdPath path;
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int offset;
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int width;
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bool init_only;
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int bits_offset;
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};
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struct Step {
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std::string bits;
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};
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std::string filename;
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std::vector<Clock> clocks;
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std::vector<Signal> signals;
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std::vector<Step> steps;
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ReadWitness(const std::string &filename);
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RTLIL::Const get_bits(int t, int bits_offset, int width) const;
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};
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template<typename D, typename T>
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void witness_hierarchy_recursion(IdPath &path, int hdlname_mode, RTLIL::Module *module, D data, T &callback)
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{
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auto const &const_path = path;
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size_t path_size = path.size();
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for (auto wire : module->wires())
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{
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auto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : wire->get_hdlname_attribute();
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for (auto item : hdlname)
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path.push_back("\\" + item);
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if (hdlname.size() == 1 && path.back() == wire->name)
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hdlname.clear();
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if (!hdlname.empty())
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callback(const_path, WitnessHierarchyItem(module, wire), data);
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path.resize(path_size);
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if (hdlname.empty() || hdlname_mode <= 0) {
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path.push_back(wire->name);
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callback(const_path, WitnessHierarchyItem(module, wire), data);
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path.pop_back();
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}
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}
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for (auto cell : module->cells())
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{
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Module *child = module->design->module(cell->type);
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if (child == nullptr)
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continue;
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auto hdlname = hdlname_mode < 0 ? std::vector<std::string>() : cell->get_hdlname_attribute();
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for (auto item : hdlname)
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path.push_back("\\" + item);
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if (hdlname.size() == 1 && path.back() == cell->name)
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hdlname.clear();
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if (!hdlname.empty()) {
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D child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);
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witness_hierarchy_recursion<D, T>(path, 1, child, child_data, callback);
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}
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path.resize(path_size);
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if (hdlname.empty() || hdlname_mode <= 0) {
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path.push_back(cell->name);
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D child_data = callback(const_path, WitnessHierarchyItem(module, cell), data);
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witness_hierarchy_recursion<D, T>(path, hdlname.empty() ? hdlname_mode : -1, child, child_data, callback);
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path.pop_back();
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}
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}
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for (auto mem : Mem::get_all_memories(module)) {
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std::vector<std::string> hdlname;
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if (hdlname_mode >= 0 && mem.cell != nullptr)
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hdlname = mem.cell->get_hdlname_attribute();
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for (auto item : hdlname)
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path.push_back("\\" + item);
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if (hdlname.size() == 1 && path.back() == mem.cell->name)
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hdlname.clear();
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if (!hdlname.empty()) {
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callback(const_path, WitnessHierarchyItem(module, &mem), data);
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}
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path.resize(path_size);
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if (hdlname.empty() || hdlname_mode <= 0) {
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path.push_back(mem.memid);
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callback(const_path, WitnessHierarchyItem(module, &mem), data);
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path.pop_back();
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if (mem.cell != nullptr && mem.cell->name != mem.memid) {
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path.push_back(mem.cell->name);
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callback(const_path, WitnessHierarchyItem(module, &mem), data);
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path.pop_back();
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}
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}
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}
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}
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template<typename D, typename T>
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void witness_hierarchy(RTLIL::Module *module, D data, T callback)
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{
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IdPath path;
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witness_hierarchy_recursion<D, T>(path, 0, module, data, callback);
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}
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YOSYS_NAMESPACE_END
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#endif
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