mirror of https://github.com/YosysHQ/yosys.git
mem: only import attributes from ports if the memory doesn't have them yet
This commit is contained in:
parent
080da693d1
commit
f9ab6e147a
|
@ -149,7 +149,8 @@ void Mem::emit() {
|
|||
wr_port_xlat.push_back(i);
|
||||
for (auto &port : rd_ports) {
|
||||
for (auto attr: port.attributes)
|
||||
cell->attributes.insert(attr);
|
||||
if (!cell->has_attribute(attr.first))
|
||||
cell->attributes.insert(attr);
|
||||
if (port.cell) {
|
||||
module->remove(port.cell);
|
||||
port.cell = nullptr;
|
||||
|
@ -213,7 +214,8 @@ void Mem::emit() {
|
|||
cell->setPort(ID::RD_DATA, rd_data);
|
||||
for (auto &port : wr_ports) {
|
||||
for (auto attr: port.attributes)
|
||||
cell->attributes.insert(attr);
|
||||
if (!cell->has_attribute(attr.first))
|
||||
cell->attributes.insert(attr);
|
||||
if (port.cell) {
|
||||
module->remove(port.cell);
|
||||
port.cell = nullptr;
|
||||
|
@ -251,7 +253,8 @@ void Mem::emit() {
|
|||
cell->setPort(ID::WR_DATA, wr_data);
|
||||
for (auto &init : inits) {
|
||||
for (auto attr: init.attributes)
|
||||
cell->attributes.insert(attr);
|
||||
if (!cell->has_attribute(attr.first))
|
||||
cell->attributes.insert(attr);
|
||||
if (init.cell) {
|
||||
module->remove(init.cell);
|
||||
init.cell = nullptr;
|
||||
|
|
Loading…
Reference in New Issue