mirror of https://github.com/YosysHQ/yosys.git
kernel/mem: Use delayed removal for inits as well.
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6d7d9ab077
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0565c642a0
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@ -76,6 +76,17 @@ void Mem::emit() {
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wr_left.push_back(i);
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}
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}
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std::vector<int> init_left;
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for (int i = 0; i < GetSize(inits); i++) {
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auto &init = inits[i];
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if (init.removed) {
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if (init.cell) {
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module->remove(init.cell);
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}
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} else {
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init_left.push_back(i);
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}
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}
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for (int i = 0; i < GetSize(rd_left); i++)
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if (i != rd_left[i])
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std::swap(rd_ports[i], rd_ports[rd_left[i]]);
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@ -84,6 +95,10 @@ void Mem::emit() {
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if (i != wr_left[i])
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std::swap(wr_ports[i], wr_ports[wr_left[i]]);
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wr_ports.resize(GetSize(wr_left));
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for (int i = 0; i < GetSize(init_left); i++)
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if (i != init_left[i])
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std::swap(inits[i], inits[init_left[i]]);
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inits.resize(GetSize(init_left));
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// for future: handle transparency mask here
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@ -264,14 +279,14 @@ void Mem::emit() {
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void Mem::clear_inits() {
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for (auto &init : inits)
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if (init.cell)
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module->remove(init.cell);
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inits.clear();
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init.removed = true;
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}
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Const Mem::get_init_data() const {
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Const init_data(State::Sx, width * size);
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for (auto &init : inits) {
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if (init.removed)
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continue;
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int offset = (init.addr.as_int() - start_offset) * width;
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for (int i = 0; i < GetSize(init.data); i++)
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if (0 <= i+offset && i+offset < GetSize(init_data))
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@ -65,10 +65,11 @@ struct MemWr : RTLIL::AttrObject {
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};
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struct MemInit : RTLIL::AttrObject {
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bool removed;
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Cell *cell;
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Const addr;
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Const data;
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MemInit() : cell(nullptr) {}
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MemInit() : removed(false), cell(nullptr) {}
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};
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struct Mem : RTLIL::AttrObject {
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