mirror of https://github.com/YosysHQ/yosys.git
Add some more reserve calls to RTLIL::Const
This results in a slight ~0.22% total speedup synthesizing vexriscv
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a7e7a9f485
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349c0ff0a7
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@ -207,6 +207,7 @@ RTLIL::Const::Const()
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RTLIL::Const::Const(std::string str)
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{
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flags = RTLIL::CONST_FLAG_STRING;
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bits.reserve(str.size() * 8);
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for (int i = str.size()-1; i >= 0; i--) {
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unsigned char ch = str[i];
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for (int j = 0; j < 8; j++) {
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@ -219,6 +220,7 @@ RTLIL::Const::Const(std::string str)
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RTLIL::Const::Const(int val, int width)
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{
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flags = RTLIL::CONST_FLAG_NONE;
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bits.reserve(width);
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for (int i = 0; i < width; i++) {
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bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
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val = val >> 1;
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@ -228,6 +230,7 @@ RTLIL::Const::Const(int val, int width)
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RTLIL::Const::Const(RTLIL::State bit, int width)
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{
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flags = RTLIL::CONST_FLAG_NONE;
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bits.reserve(width);
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for (int i = 0; i < width; i++)
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bits.push_back(bit);
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}
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@ -235,6 +238,7 @@ RTLIL::Const::Const(RTLIL::State bit, int width)
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RTLIL::Const::Const(const std::vector<bool> &bits)
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{
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flags = RTLIL::CONST_FLAG_NONE;
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this->bits.reserve(bits.size());
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for (const auto &b : bits)
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this->bits.emplace_back(b ? State::S1 : State::S0);
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}
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@ -242,6 +246,7 @@ RTLIL::Const::Const(const std::vector<bool> &bits)
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RTLIL::Const::Const(const RTLIL::Const &c)
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{
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flags = c.flags;
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this->bits.reserve(c.size());
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for (const auto &b : c.bits)
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this->bits.push_back(b);
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}
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