Commit Graph

1637 Commits

Author SHA1 Message Date
Archie c8cd4f468a Adding testcase for issue 3374 2022-06-22 00:34:49 +01:00
George Rennie 5dfad5101d chformal: Rename -coverprecond to -coverenable 2022-06-18 18:28:12 +01:00
Jannis Harder e39c422734 chformal: Test -coverprecond and reuse the src attribute 2022-06-18 18:19:26 +01:00
Jannis Harder ac22f1764d smt2: emit smtlib2_comb_expr outputs after all inputs 2022-06-07 19:06:45 +02:00
Jacob Lifshay 0b0123e003 don't use sed -i because it won't work on macos 2022-06-03 01:09:57 -07:00
Jacob Lifshay b7c19b1c88 smtlib2_module: try to fix test on macos 2022-06-02 23:12:07 -07:00
Jacob Lifshay cd57c5adb3 smt2: Add smtlib2_comb_expr attribute to allow user-selected smtlib2 expressions 2022-06-02 22:37:29 -07:00
Zachary Snow a650d9079f verilog: fix width/sign detection for functions 2022-05-30 16:45:39 -04:00
Jannis Harder 4bfaaea0d5 verilog: fix size and signedness of array querying functions
genrtlil.cc and simplify.cc had inconsistent and slightly broken
handling of signedness for array querying functions. These functions are
defined to return a signed result. Simplify always produced an unsigned
and genrtlil always a signed 32-bit result ignoring the context.

Includes tests for the the relvant edge cases for context dependent
conversions.
2022-05-30 09:11:31 -04:00
Jannis Harder b75fa62e9b verilog: fix $past's signedness 2022-05-25 16:32:08 -04:00
Jannis Harder cffec1f95f verilog: fix signedness when removing unreachable cases 2022-05-24 23:03:31 -04:00
Marcelina Kościelnicka 606f1637ae Add memory_bmux2rom pass. 2022-05-18 22:48:55 +02:00
Marcelina Kościelnicka 982a11c709 Add memory_libmap tests. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka 9d11575856 efinix: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka d7dc2313b9 ice40: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka 3b2f95953c xilinx: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka 0a8eaca322 nexus: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka a04b025abf ecp5: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka 9450f308f0 proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
Jannis Harder 2864f2826a
Merge pull request #3314 from jix/sva_value_change_logic_wide
verific: Use new value change logic also for $stable of wide signals.
2022-05-16 16:15:04 +02:00
Marcelina Kościelnicka 990c9b8e11 Add proc_rom pass. 2022-05-13 00:37:14 +02:00
Jannis Harder fada77b8cf verific: Use new value change logic also for $stable of wide signals.
I missed this in the previous PR.
2022-05-11 13:05:27 +02:00
Jannis Harder 587e09d551
Merge pull request #3305 from jix/sva_value_change_logic
verific: Improve logic generated for SVA value change expressions
2022-05-09 16:40:34 +02:00
Jannis Harder 5ca2ee0c31
Merge pull request #3297 from jix/sva_nested_clk_else
verific: Fix conditions of SVAs with explicit clocks within procedures
2022-05-09 16:07:39 +02:00
Jannis Harder a855d62b42 verific: Improve logic generated for SVA value change expressions
The previously generated logic assumed an unconstrained past value in
the initial state and did not handle 'x values. While the current formal
verification flow uses 2-valued logic, SVA value change expressions
require a past value of 'x during the initial state to behave in the
expected way (i.e. to consider both an initial 0 and an initial 1 as
$changed and an initial 1 as $rose and an initial 0 as $fell).

This patch now generates logic that at the same time

	a) provides the expected behavior in a 2-valued logic setting, not
	   depending on any dont-care optimizations, and

	b) properly handles 'x values in yosys simulation
2022-05-09 15:04:01 +02:00
Miodrag Milanovic 600079e281 Fix running sva tests 2022-05-09 09:01:57 +02:00
Marcelina Kościelnicka 77b1dfd8c3 opt_mem: Remove constant-value bit lanes. 2022-05-07 23:13:16 +02:00
Jannis Harder 96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
2022-05-03 14:13:08 +02:00
Zachary Snow bf15dbd0f7 sv: fix always_comb auto nosync for nested and function blocks 2022-04-05 14:43:48 -06:00
Jannis Harder ca5b910296 opt_merge: Add `-keepdc` option required for formal verification
The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.

The keepdc option of `opt` is passed along to `opt_merge` now.
2022-04-01 21:03:20 +02:00
Miodrag Milanovic bbf65702a1 Fix valgrind tests when using verific 2022-03-30 17:25:53 +02:00
Miodrag Milanovic 27c5bafc95 Proper example code 2022-03-14 15:39:11 +01:00
Lofty 9f7a55c99f intel_alm: M10K write-enable is negative-true 2022-03-09 20:18:06 +00:00
Miodrag Milanović c3124023e4
Merge pull request #3207 from nakengelhardt/json_escape_quotes
fix handling of escaped chars in json backend and frontend (mostly)
2022-03-04 13:57:32 +01:00
N. Engelhardt 8fd1b06249 fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
Miodrag Milanovic 21baf48e04 test dlatchsr and adlatch 2022-02-16 13:58:51 +01:00
Miodrag Milanovic 271ac28b41 Added test cases 2022-02-16 13:27:59 +01:00
Zachary Snow 15a4e900b2 verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
Kamil Rakoczy 68c67c40ec
Fix access to whole sub-structs (#3086)
* Add support for accessing whole struct
* Update tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-02-14 14:34:20 +01:00
Zachary Snow 15eb66b99d verilog: fix dynamic dynamic range asgn elab 2022-02-11 22:54:55 +01:00
Zachary Snow 90bb47d181 verilog: fix const func eval with upto variables 2022-02-11 21:01:51 +01:00
Marcelina Kościelnicka f61f2a4078 gowin: Fix LUT RAM inference, add more models. 2022-02-09 09:04:34 +01:00
Miodrag Milanović d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim
Add co-simulation in sim pass
2022-02-07 16:36:43 +01:00
Miodrag Milanovic 6db23de7b1 bug fix and cleanups 2022-02-04 10:01:06 +01:00
Miodrag Milanovic 7ef6da4c7d Add test cases for co-simulation 2022-02-02 13:22:44 +01:00
Marcelina Kościelnicka 07a657fb0c opt_reduce: Add $bmux and $demux optimization patterns. 2022-01-30 03:37:52 +01:00
Miodrag Milanović 4525e419f6
Merge pull request #3120 from Icenowy/anlogic-bram
anlogic: support BRAM mapping
2022-01-19 08:49:58 +01:00
Zachary Snow aa35f24290 sv: auto add nosync to certain always_comb local vars
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
2022-01-07 22:53:22 -07:00
Zachary Snow 828e85068f sv: fix size cast internal expression extension 2022-01-07 21:21:02 -07:00
Zachary Snow 66447e8faf logger: fix unmatched expected warnings and errors
- Prevent unmatched expected error patterns from self-matching
- Prevent infinite recursion on unmatched expected warnings
- Always print the error message for unmatched error patterns
- Add test coverage for all unmatched message types
- Add test coverage for excess matched logs and warnings
2022-01-04 13:39:34 -07:00
Zachary Snow e0e4dfb55e fix iverilog compatibility for new case expr tests 2022-01-03 12:11:41 -07:00
Zachary Snow 207af4196b fixup verilog doubleslash test
- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again
2022-01-03 08:17:46 -07:00
Zachary Snow 8c509a5659 sv: fix size cast clipping expression width 2022-01-03 08:17:35 -07:00
Marcelina Kościelnicka f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports.
Fixes #3117.
2021-12-20 18:40:14 +01:00
Zachary Snow 7608985d2c fix width detection of array querying function in case and case item expressions
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
2021-12-17 21:22:08 -07:00
Icenowy Zheng c2b7ad3b28 anlogic: support BRAM mapping
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-17 20:28:22 +08:00
Thomas Sailer 4cd2f03e36 preprocessor: do not destroy double slash escaped identifiers
The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'

This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
2021-12-15 18:06:02 -07:00
Claire Xenia Wolf d6e4d3f1ba Fix the tests we just broke
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-10 00:22:37 +01:00
Miodrag Milanovic d65942b9ac Add gitignore for gatemate 2021-12-03 09:56:37 +01:00
Lofty 77327b2544 sta: very crude static timing analysis pass
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2021-11-25 17:20:27 +01:00
Kamil Rakoczy fdb19a5b3a
Support parameters using struct as a wiretype (#3050)
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-11-16 10:59:54 +01:00
Patrick Urban 81964d6d6f synth_gatemate: Update pass
* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
2021-11-13 21:53:25 +01:00
Patrick Urban 97d03c2b3b synth_gatemate: Apply new test practice with assert-max 2021-11-13 21:53:25 +01:00
Patrick Urban 76bf96d310 synth_gatemate: Fix fsm test 2021-11-13 21:53:25 +01:00
Patrick Urban acb993b27b Allow initial blocks to be disabled during tests
Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
2021-11-13 21:53:25 +01:00
Patrick Urban 240d289fff synth_gatemate: Initial implementation
Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-11-13 21:53:25 +01:00
Marcelina Kościelnicka 15b0d717ed iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
Marcelina Kościelnicka 0b31cb598e dfflegalize: Add tests for aldff lowering. 2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka 54c79af64f dfflegalize: Add tests targetting aldff. 2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka 0a0df8d38c dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka e64456f920 extract_reduce: Refactor and fix input signal construction.
Fixes #3047.
2021-10-21 04:10:01 +02:00
Claire Xenia Wolf 83887495b8 Fixes in vcdcd.pl for newer Perl versions
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-19 10:56:43 +02:00
Marcelina Kościelnicka dc8da76282 Fix a regression from #3035. 2021-10-08 15:44:07 +02:00
Marcelina Kościelnicka 4e70c30775 FfData: some refactoring.
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
2021-10-07 04:24:06 +02:00
Claire Xen 0146d83ed8
Merge pull request #3014 from YosysHQ/claire/fix-vgtest
Fix "make vgtest"
2021-09-24 17:50:34 +02:00
Claire Xenia Wolf 15fb0107dc Fix "make vgtest" so it runs to the end (but now it fails ;)
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-09-23 14:54:28 +02:00
Zachary Snow d6fe6d4fb6 sv: support wand and wor of data types
This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
2021-09-21 14:52:28 -04:00
Zachary Snow 6b7267b849 verilog: fix multiple AST_PREFIX scope resolution issues
- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
2021-09-21 12:10:59 -04:00
Eddie Hung 96b6410dcb
abc9: make re-entrant (#2993)
* Add testcase

* Cleanup some state at end of abc9

* Re-assign abc9_box_id from scratch

* Suppress delete unless prep_bypass did something
2021-09-09 10:06:31 -07:00
Eddie Hung 65316ec926
abc9: holes module to instantiate cells with NEW_ID (#2992)
* Add testcase

* holes module to instantiate cells with NEW_ID
2021-09-09 10:06:20 -07:00
Eddie Hung f03e2c30aa
abc9: replace cell type/parameters if derived type already processed (#2991)
* Add close bracket

* Add testcase

* Replace cell type/param if in unmap_design

* Improve abc9_box error message too

* Update comment as per review
2021-09-09 10:05:55 -07:00
Zachary Snow b2e9717419 sv: support declaration in generate for initialization
This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
2021-08-31 12:34:55 -06:00
Zachary Snow f0a52e3dd2 sv: support declaration in procedural for initialization
In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
2021-08-30 15:19:21 -06:00
Marcelina Kościelnicka 62d41d4639 opt_clean: Make the init attribute follow the FF's Q.
Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire.  This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.

Part of another jab at #2920.
2021-08-22 15:38:29 +02:00
Pepijn de Vos c2d358484f
Gowin: deal with active-low tristate (#2971)
* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests
2021-08-20 21:21:06 +02:00
Marcelina Kościelnicka faacc7ad89 proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
Fixes #2962.
2021-08-14 15:26:11 +02:00
Marcelina Kościelnicka f791328506 Add opt_mem_widen pass.
If all of us are wide, then none of us are!
2021-08-14 01:06:23 +02:00
Marcelina Kościelnicka 1f74ec3535 memory_share: Add -nosat and -nowiden options.
This unlocks wide port recognition by default.
2021-08-14 00:09:04 +02:00
Marcelina Kościelnicka 9fdedf4d1c memory_dff: Recognize soft transparency logic. 2021-08-13 23:08:32 +02:00
Marcelina Kościelnicka 616ace2d92 Add new opt_mem_priority pass. 2021-08-13 11:58:52 +02:00
Brett Witherspoon 979053855c sv: improve support for wire and var with user-defined types
- User-defined types must be data types. Using a net type (e.g. wire) is
  a syntax error.
- User-defined types without a net type are always variables (i.e.
  logic).
- Nets and variables can now be explicitly declared using user-defined
  types:

    typedef logic [1:0] W;
    wire W w;

    typedef logic [1:0] V;
    var V v;

Fixes #2846
2021-08-12 22:41:41 -06:00
Marcelina Kościelnicka b98376884e test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.
These parts keep rereading a Verilog module, then using chparam
to test it with various parameter combinations.  Since the default
parameters are on the large side, this spends a lot of time
needlessly elaborating the default parametrization that will then
be discarded.  Fix it with -deref and manual hierarchy call.

Shaves 30s off the test time on my machine.
2021-08-11 14:52:38 +02:00
Marcelina Kościelnicka 72d86c327e memory_dff: Recognize read ports with reset / initial value. 2021-08-11 14:17:48 +02:00
Marcelina Kościelnicka 24027b5446 proc_memwr: Use the v2 memwr cell. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka 98003430d6 opt_merge: Use FfInitVals.
Partial #2920 fix.
2021-08-08 01:19:22 +02:00
Zachary Snow c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
2021-07-29 20:55:59 -04:00
Zachary Snow 4fec3a85cd genrtlil: add width detection for AST_PREFIX nodes 2021-07-29 20:55:31 -04:00
Marcelina Kościelnicka 54e75129e5 opt_lut: Allow more than one -dlogic per cell type.
Fixes #2061.
2021-07-29 17:30:07 +02:00
Zachary Snow 3156226233 verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
Marcelina Kościelnicka 8bdc019730 verilog: Emit $meminit_v2 cell.
Fixes #2447.
2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka 436d42c00c opt_expr: Propagate constants to port connections.
This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value.  This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
2021-07-27 20:44:26 +02:00
Rupert Swarbrick 414154dd27 Add support for parsing the SystemVerilog 'bind' construct
This doesn't do anything useful yet: the patch just adds support for
the syntax to the lexer and parser and adds some tests to check the
syntax parses properly. This generates AST nodes, but doesn't yet
generate RTLIL.

Since our existing hierarchical_identifier parser doesn't allow bit
selects (so you can't do something like foo[1].bar[2].baz), I've also
not added support for a trailing bit select (the "constant_bit_select"
non-terminal in "bind_target_instance" in the spec). If we turn out to
need this in future, we'll want to augment hierarchical_identifier and
its other users too.

Note that you can't easily use the BNF from the spec:

    bind_directive ::=
        "bind" bind_target_scope [ : bind_target_instance_list]
               bind_instantiation ;
      | "bind" bind_target_instance bind_instantiation ;

even if you fix the lookahead problem, because code like this matches
both branches in the BNF:

    bind a b b_i (.*);

The problem is that 'a' could either be a module name or a degenerate
hierarchical reference. This seems to be a genuine syntactic
ambiguity, which the spec resolves (p739) by saying that we have to
wait until resolution time (the hierarchy pass) and take whatever is
defined, treating 'a' as an instance name if it names both an instance
and a module.

To keep the parser simple, it currently accepts this invalid syntax:

    bind a.b : c d e (.*);

This is invalid because we're in the first branch of the BNF above, so
the "a.b" term should match bind_target_scope: a module or interface
identifier, not an arbitrary hierarchical identifier.

This will fail in the hierarchy pass (when it's implemented in a
future patch).
2021-07-16 09:31:39 -04:00
Zachary Snow a9c8ca21d5 sv: fix two struct access bugs
- preserve signedness of struct members
- fix initial width detection of struct members (e.g., in case expressions)
2021-07-15 11:57:20 -04:00
Rupert Swarbrick 1aab608cff Add a test for interfaces on modules loaded on-demand 2021-07-14 22:54:50 -04:00
Zachary Snow f2c2d73f36 sv: fix up end label checking
- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
2021-06-16 21:48:05 -04:00
Marcelina Kościelnicka 438bcc68c0 Add regression test for #2824. 2021-06-11 12:06:35 +01:00
Claire Xen 55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
Claire Xenia Wolf 0ff4fb1eb3 More deadname stuff
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:40:33 +02:00
Claire Xenia Wolf a734face3a More deadname stuff 2021-06-09 12:33:41 +02:00
Claire Xenia Wolf 0ada13cbe2 Use HTTPS for website links, gatecat email
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
2021-06-09 12:16:56 +02:00
Claire Xenia Wolf 92e705cb51 Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
Zachary Snow 2e697f5655 verilog: check for module scope identifiers during width detection
The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().
2021-06-08 15:03:16 -04:00
Zachary Snow c79fbfe0a1 mem2reg: tolerate out of bounds constant accesses
This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-06-08 15:02:57 -04:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Zachary Snow 8cfed1a979 sv: support tasks and functions within packages 2021-06-01 13:17:41 -04:00
Marcelina Kościelnicka 13b901bf1c memory_map: Improve start_offset handling.
Fixes #2775.
2021-05-31 17:45:21 +02:00
Marcelina Kościelnicka 18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg.
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
2021-05-25 22:42:03 +02:00
Zachary Snow 0795b3ec07 verilog: fix case expression sign and width handling
- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
2021-05-25 16:16:46 -04:00
Zachary Snow 15f35d6754 sv: support remaining assignment operators
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
2021-05-25 16:15:57 -04:00
Marcelina Kościelnicka 5628f5a88f opt_mem_feedback: Respect write port priority. 2021-05-25 15:59:41 +02:00
Marcelina Kościelnicka 835688bf80 opt_mem_feedback: Rewrite feedback path finding logic.
Fixes #2766.
2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka 1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff.
Fixes #1854.
2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka a23d9409e7 opt_mem: Remove write ports with const-0 EN.
Fixes #2765.
2021-05-23 14:30:56 +02:00
Marcelina Kościelnicka 4240498f71 tests/blif: Add missing gitignore 2021-05-20 12:49:51 +02:00
gatecat 34a08750fa intel_alm: Fix illegal carry chains
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat eb106732d9 intel_alm: Add global buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat 5dba138c87 intel_alm: Add IO buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
Zachary Snow 4452080861 sv: check validity of package end label 2021-05-10 14:37:32 -04:00
Marcelina Kościelnicka 32a0ce9d68 blif: Use library cells' start_offset and upto for wideports.
Fixes #2729.
2021-05-08 15:50:03 +02:00
Marcelina Kościelnicka 5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. 2021-05-04 21:03:40 +02:00
Claire Xenia Wolf 8aee80040d Add default assignments to SB_LUT4
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-04-20 12:46:21 +02:00
Lofty dce037a62c quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
Zachary Snow 0ccc7229c0 preproc: test coverage for #2712 2021-03-30 12:23:18 -04:00
Eddie Hung 8c5f379435
abc9: uniquify blackboxes like whiteboxes (#2695)
* abc9_ops: uniquify blackboxes too

* abc9_ops: update comment

* abc9_ops: allow bypass for param-less blackboxes

* Add tests
2021-03-29 22:02:06 -07:00
Eddie Hung 55dc5a4e4f
abc9: fix SCC issues (#2694)
* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
2021-03-29 22:01:57 -07:00
Marcelina Kościelnicka 4a35f244aa quicklogic: Add .gitignore file for test outputs. 2021-03-23 17:35:00 +01:00
Xiretza 92d5550a90 verilog: check entire user type stack for type definition 2021-03-21 19:35:13 -04:00
Zachary Snow 4f4e70876f sv: allow typenames as function return types 2021-03-19 12:08:43 -04:00
Lofty f4298b057a quicklogic: PolarPro 3 support
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
Marcelina Kościelnicka 8740fdf1d7 ast: Use better parameter serialization for paramod names.
Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
2021-03-18 00:52:00 +01:00
gatecat cae905f551 Blackbox all whiteboxes after synthesis
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Zachary Snow f71c2dcca6 sv: carry over global typedefs from previous files
This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
2021-03-17 15:53:52 -04:00
Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs
From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
2021-03-17 11:44:03 -04:00
gatecat dd6d34f461 blackbox: Include whiteboxed modules
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
Zachary Snow 4f187d53c5 verilog: support module scope identifiers in parametric modules 2021-03-16 11:01:30 -04:00
Marcelina Kościelnicka a55bf6375b proc_arst: Add special-casing of clock signal in conditionals.
The already-existing special case for conditionals on clock has been
remade as follows:

- now triggered for the last remaining edge trigger after all others
  have been converted to async reset, not just when there is only one
  sync rule in the first place
- does not require all contained assignments to be constant, as opposed
  to a reset conditional — merely const-folds the condition

In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).

Fixes #2656.
2021-03-15 17:17:29 +01:00
Marcelina Kościelnicka 3af871f969 opt_clean: Remove init attribute bits together with removed DFFs.
Fixes #2546.
2021-03-15 17:16:53 +01:00
Marcelina Kościelnicka f965b3fa54 rtlil: Disallow 0-width chunks in SigSpec.
Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.

Also fix another minor issue with possible non-canonical SigSpec.

Fixes #2623.
2021-03-15 17:16:24 +01:00