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fix width detection of array querying function in case and case item expressions 

I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
This commit is contained in:
Zachary Snow 2021-12-15 18:15:09 -07:00 committed by Zachary Snow
parent 60c3ea367c
commit 7608985d2c
5 changed files with 50 additions and 2 deletions
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2
CHANGELOG
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@ -14,6 +14,8 @@ Yosys 0.11 .. Yosys 0.12
* SystemVerilog
- Support parameters using struct as a wiretype
- Fixed regression preventing the use array querying functions in case
expressions and case item expressions
* New commands and options
- Added "-genlib" option to "abc" pass

5
frontends/ast/genrtlil.cc
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@ -1087,6 +1087,11 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
}
break;
}
if (str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right") {
width_hint = 32;
sign_hint = true;
break;
}
if (current_scope.count(str))
{
// This width detection is needed for function calls which are

2
frontends/ast/simplify.cc
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@ -1389,8 +1389,6 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (const_fold && type == AST_CASE)
{
int width_hint;
bool sign_hint;
detectSignWidth(width_hint, sign_hint);
while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { }
if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {

11
tests/simple/case_expr_extend.sv Normal file
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@ -0,0 +1,11 @@
module top(
output logic [5:0] out
);
always_comb begin
out = '0;
case (1'b1 << 1)
2'b10: out = '1;
default: out = '0;
endcase
end
endmodule

32
tests/simple/case_expr_query.sv Normal file
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@ -0,0 +1,32 @@
module top(
output logic [5:0] out
);
always_comb begin
out = '0;
case ($bits (out)) 6:
case ($size (out)) 6:
case ($high (out)) 5:
case ($low (out)) 0:
case ($left (out)) 5:
case ($right(out)) 0:
case (6) $bits (out):
case (6) $size (out):
case (5) $high (out):
case (0) $low (out):
case (5) $left (out):
case (0) $right(out):
out = '1;
endcase
endcase
endcase
endcase
endcase
endcase
endcase
endcase
endcase
endcase
endcase
endcase
end
endmodule