verilog: support for time scale delay values

CHANGELOG

@@ -10,6 +10,7 @@ Yosys 0.14 .. Yosys 0.14-dev
       reversed dimensions
     - Fixed elaboration of dynamic range assignments where the vector is
       reversed or is not zero-indexed
+    - Added frontend support for time scale delay values (e.g., `#1ns`)
 
  * SystemVerilog
     - Added support for accessing whole sub-structures in expressions

frontends/verilog/verilog_lexer.l

@@ -128,6 +128,11 @@ static bool isUserType(std::string &s)
 %x IMPORT_DPI
 %x BASED_CONST
 
+UNSIGNED_NUMBER [0-9][0-9_]*
+FIXED_POINT_NUMBER_DEC [0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)?
+FIXED_POINT_NUMBER_NO_DEC [0-9][0-9_]*[eE][-+]?[0-9_]+
+TIME_SCALE_SUFFIX [munpf]?s
+
 %%
 	// Initialise comment_caller to something to avoid a "maybe undefined"
 	// warning from GCC.
@@ -297,7 +302,7 @@ static bool isUserType(std::string &s)
 "union"   { SV_KEYWORD(TOK_UNION); }
 "packed"  { SV_KEYWORD(TOK_PACKED); }
 
-[0-9][0-9_]* {
+{UNSIGNED_NUMBER} {
 	yylval->string = new std::string(yytext);
 	return TOK_CONSTVAL;
 }
@@ -319,12 +324,12 @@ static bool isUserType(std::string &s)
 	return TOK_BASED_CONSTVAL;
 }
 
-[0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
+{FIXED_POINT_NUMBER_DEC} {
 	yylval->string = new std::string(yytext);
 	return TOK_REALVAL;
 }
 
-[0-9][0-9_]*[eE][-+]?[0-9_]+ {
+{FIXED_POINT_NUMBER_NO_DEC} {
 	yylval->string = new std::string(yytext);
 	return TOK_REALVAL;
 }
@@ -574,6 +579,10 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 	return TOK_SPECIFY_AND;
 }
 
+{UNSIGNED_NUMBER}{TIME_SCALE_SUFFIX} { return TOK_TIME_SCALE; }
+{FIXED_POINT_NUMBER_DEC}{TIME_SCALE_SUFFIX} { return TOK_TIME_SCALE; }
+{FIXED_POINT_NUMBER_NO_DEC}{TIME_SCALE_SUFFIX} { return TOK_TIME_SCALE; }
+
 <INITIAL,BASED_CONST>"/*" { comment_caller=YY_START; BEGIN(COMMENT); }
 <COMMENT>.    /* ignore comment body */
 <COMMENT>\n   /* ignore comment body */

frontends/verilog/verilog_parser.y

@@ -369,7 +369,7 @@ static void rewriteGenForDeclInit(AstNode *loop)
 %token TOK_BIT_OR_ASSIGN TOK_BIT_AND_ASSIGN TOK_BIT_XOR_ASSIGN TOK_ADD_ASSIGN
 %token TOK_SUB_ASSIGN TOK_DIV_ASSIGN TOK_MOD_ASSIGN TOK_MUL_ASSIGN
 %token TOK_SHL_ASSIGN TOK_SHR_ASSIGN TOK_SSHL_ASSIGN TOK_SSHR_ASSIGN
-%token TOK_BIND
+%token TOK_BIND TOK_TIME_SCALE
 
 %type <ast> range range_or_multirange non_opt_range non_opt_multirange
 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list non_io_wire_type io_wire_type
@@ -779,6 +779,9 @@ non_opt_delay:
 	'#' TOK_ID { delete $2; } |
 	'#' TOK_CONSTVAL { delete $2; } |
 	'#' TOK_REALVAL { delete $2; } |
+	// our `expr` doesn't have time_scale, so we need the parenthesized variant
+	'#' TOK_TIME_SCALE |
+	'#' '(' TOK_TIME_SCALE ')' |
 	'#' '(' mintypmax_expr ')' |
 	'#' '(' mintypmax_expr ',' mintypmax_expr ')' |
 	'#' '(' mintypmax_expr ',' mintypmax_expr ',' mintypmax_expr ')';

tests/verilog/delay_time_scale.ys

@@ -0,0 +1,25 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOT
+module top;
+wand x;
+`define TEST(time_scale) if (1) assign #time_scale x = 1;
+
+`TEST(1s)
+`TEST(1ms)
+`TEST(1us)
+`TEST(1ns)
+`TEST(1ps)
+`TEST(1fs)
+
+`TEST((1s))
+`TEST(( 1s))
+`TEST((1s ))
+`TEST(( 1s ))
+
+`TEST(1.0s)
+`TEST(1.1s)
+`TEST(1.0e-1s)
+`TEST(1e-1s)
+
+endmodule
+EOT