riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

intel_alm: M10K write-enable is negative-true

This commit is contained in:
Lofty 2022-03-09 16:40:32 +00:00 committed by gatecat
parent 4ccc2adbda
commit 9f7a55c99f
7 changed files with 30 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
techlibs/intel_alm/Makefile.inc
View File

@ -19,6 +19,7 @@ $(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclone
# RAM
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))

4
techlibs/intel_alm/common/bram_m10k.txt
View File

@ -1,4 +1,4 @@
bram MISTRAL_M10K
bram $__MISTRAL_M10K
init 0 # TODO: Re-enable when I figure out how BRAM init works
abits 13 @D8192x1
dbits 1 @D8192x1
@ -21,7 +21,7 @@ bram MISTRAL_M10K
endbram
match MISTRAL_M10K
match $__MISTRAL_M10K
min efficiency 5
make_transp
endmatch

16
techlibs/intel_alm/common/bram_m10k_map.v Normal file
View File

@ -0,0 +1,16 @@
// Stub to invert M10K write-enable.
module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input A1EN, B1EN;
output reg [CFG_DBITS-1:0] B1DATA;
MISTRAL_M10K #(.CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));
endmodule

2
techlibs/intel_alm/common/mem_sim.v
View File

@ -145,7 +145,7 @@ endspecify
`endif
always @(posedge CLK1) begin
if (A1EN)
if (!A1EN)
mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
if (B1EN)

9
techlibs/intel_alm/common/quartus_rename.v
View File

@ -157,6 +157,11 @@ output [CFG_DBITS-1:0] B1DATA;
// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
// you initialise the RAM cell via hex literals. If they were implemented.
// Since the MISTRAL_M10K block has an inverted write-enable (like the real hardware)
// but the Quartus primitive expects a normal write-enable, we add an inverter.
wire A1EN_N;
NOT wren_inv (.IN(A1EN), .OUT(A1EN_N));
`RAM_BLOCK #(
.operation_mode("dual_port"),
.logical_ram_name(_TECHMAP_CELLNAME_),
@ -176,10 +181,10 @@ output [CFG_DBITS-1:0] B1DATA;
.port_b_first_bit_number(0),
.port_b_address_clock("clock0"),
.port_b_read_enable_clock("clock0")
) _TECHMAP_REPLACE_ (
) ram_block (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portawe(A1EN),
.portawe(A1EN_N),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.portbre(B1EN),

3
techlibs/intel_alm/synth_intel_alm.cc
View File

@ -262,8 +262,7 @@ struct SynthIntelALMPass : public ScriptPass {
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str()));
if (help_mode || bram_type != "m10k")
run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
}
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {

3
tests/arch/intel_alm/blockram.ys
View File

@ -2,5 +2,6 @@ read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
synth_intel_alm -family cyclonev -noiopad -noclkbuf
cd sync_ram_sdp
select -assert-count 1 t:MISTRAL_NOT
select -assert-count 1 t:MISTRAL_M10K
select -assert-none t:MISTRAL_M10K %% t:* %D
select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D