Added test cases

Makefile

@@ -803,6 +803,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/various && bash run-test.sh
 	+cd tests/select && bash run-test.sh
 	+cd tests/sat && bash run-test.sh
+	+cd tests/sim && bash run-test.sh
 	+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
 	+cd tests/svtypes && bash run-test.sh $(SEEDOPT)
 	+cd tests/proc && bash run-test.sh

tests/sim/.gitignore

@@ -0,0 +1,6 @@
+*.log
+/run-test.mk
++*_synth.v
++*_testbench
+*.out
+*.fst

tests/sim/adff.v

@@ -0,0 +1,7 @@
+module adff( input d, clk, rst, output reg q );
+	always @( posedge clk, posedge rst )
+		if (rst)
+			q <= 0;
+		else
+			q <= d;
+endmodule

tests/sim/adffe.v

@@ -0,0 +1,8 @@
+module adffe( input d, clk, rst, en, output reg q );
+	always @( posedge clk, posedge rst )
+		if (rst)
+			q <= 0;
+		else
+			if (en)
+				q <= d;
+endmodule

tests/sim/adlatch.v

@@ -0,0 +1,8 @@
+module adlatch( input d, rst, en, output reg q );
+	always @* begin
+		if (rst)
+			q = 0;
+		else if (en)
+			q = d;
+	end
+endmodule

tests/sim/aldff.v

@@ -0,0 +1,7 @@
+module aldff( input [0:3] d, input [0:3] ad, input clk, aload, output reg [0:3] q );
+	always @( posedge clk, posedge aload)
+		if (aload)
+			q <= ad;
+		else
+			q <= d;
+endmodule

tests/sim/aldffe.v

@@ -0,0 +1,8 @@
+module aldffe( input [0:3] d, input [0:3] ad, input clk, aload, en, output reg [0:3] q );
+	always @( posedge clk, posedge aload)
+		if (aload)
+			q <= ad;
+		else
+			if (en)
+				q <= d;
+endmodule

tests/sim/dff.v

@@ -0,0 +1,4 @@
+module dff( input d, clk, output reg q );
+	always @( posedge clk )
+		q <= d;
+endmodule

tests/sim/dffe.v

@@ -0,0 +1,5 @@
+module dffe( input clk, en, d, output reg q );
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule

tests/sim/dffsr.v

@@ -0,0 +1,9 @@
+module dffsr( input clk, d, clr, set, output reg q );
+	always @( posedge clk, posedge set, posedge clr)
+		if ( clr )
+			q <= 0;
+		else if (set)
+			q <= 1;
+		else
+			q <= d;
+endmodule

tests/sim/dlatch.v

@@ -0,0 +1,6 @@
+module dlatch( input d, en, output reg q );
+	always @* begin
+		if ( en )
+			q = d;
+	end
+endmodule

tests/sim/run-test.sh

@@ -0,0 +1,12 @@
+#!/usr/bin/env bash
+set -eu
+source ../gen-tests-makefile.sh
+echo "Generate FST for sim models"
+find tb/* -name tb*.v | while read name; do
+    test_name=$(basename -s .v $name)
+    echo "Test $test_name"
+    verilog_name=${test_name:3}.v
+    iverilog -o tb/$test_name.out $name $verilog_name
+    ./tb/$test_name.out -fst
+done
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"

tests/sim/sdff.v

@@ -0,0 +1,7 @@
+module sdff( input d, clk, rst, output reg q );
+	always @( posedge clk)
+		if (rst)
+			q <= 0;
+		else
+			q <= d;
+endmodule

tests/sim/sdffce.v

@@ -0,0 +1,8 @@
+module sdffce( input d, clk, rst, en, output reg q );
+	always @( posedge clk)
+		if(en)
+			if (rst)
+				q <= 0;
+			else
+				q <= d;
+endmodule

tests/sim/sdffe.v

@@ -0,0 +1,8 @@
+module sdffe( input d, clk, rst, en, output reg q );
+	always @( posedge clk)
+		if (rst)
+			q <= 0;
+		else
+			if (en)
+				q <= d;
+endmodule

tests/sim/sim_adff.ys

@@ -0,0 +1,6 @@
+read_verilog adff.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$adff
+sim -clock clk -r tb_adff.fst -scope tb_adff.uut -sim-cmp adff

tests/sim/sim_adffe.ys

@@ -0,0 +1,6 @@
+read_verilog adffe.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$adffe
+sim -clock clk -r tb_adffe.fst -scope tb_adffe.uut -sim-cmp adffe

tests/sim/sim_adlatch.ys

@@ -0,0 +1,6 @@
+read_verilog adlatch.v
+synth
+#TODO: adlatch is not emited
+stat
+#select -assert-count 1 t:$adlatch
+sim -r tb_adlatch.fst -scope tb_adlatch.uut -sim-cmp adlatch

tests/sim/sim_aldff.ys

@@ -0,0 +1,6 @@
+read_verilog aldff.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$aldff
+sim -clock clk -r tb_aldff.fst -scope tb_aldff.uut -sim-cmp aldff

tests/sim/sim_aldffe.ys

@@ -0,0 +1,6 @@
+read_verilog aldffe.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$aldffe
+sim -clock clk -r tb_aldffe.fst -scope tb_aldffe.uut -sim-cmp aldffe

tests/sim/sim_dff.ys

@@ -0,0 +1,6 @@
+read_verilog dff.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$dff
+sim -clock clk -r tb_dff.fst -scope tb_dff.uut -sim-cmp dff

tests/sim/sim_dffe.ys

@@ -0,0 +1,6 @@
+read_verilog dffe.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$dffe
+sim -clock clk -r tb_dffe.fst -scope tb_dffe.uut -sim-cmp dffe

tests/sim/sim_dffsr.ys

@@ -0,0 +1,6 @@
+read_verilog dffsr.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$dffsr
+sim -clock clk -r tb_dffsr.fst -scope tb_dffsr.uut -sim-cmp dffsr

tests/sim/sim_dlatch.ys

@@ -0,0 +1,6 @@
+read_verilog dlatch.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$dlatch
+sim -r tb_dlatch.fst -scope tb_dlatch.uut -sim-cmp dlatch

tests/sim/sim_sdff.ys

@@ -0,0 +1,6 @@
+read_verilog sdff.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$sdff
+sim -clock clk -r tb_sdff.fst -scope tb_sdff.uut -sim-cmp sdff

tests/sim/sim_sdffce.ys

@@ -0,0 +1,6 @@
+read_verilog sdffce.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$sdffce
+sim -clock clk -r tb_sdffce.fst -scope tb_sdffce.uut -sim-cmp sdffce

tests/sim/sim_sdffe.ys

@@ -0,0 +1,6 @@
+read_verilog sdffe.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$sdffe
+sim -clock clk -r tb_sdffe.fst -scope tb_sdffe.uut -sim-cmp sdffe

tests/sim/tb/tb_adff.v

@@ -0,0 +1,40 @@
+`timescale 1ns/1ns 
+module tb_adff();
+	reg clk = 0;
+	reg rst = 0;
+	reg d = 0;
+	wire q;
+
+	adff uut(.clk(clk),.d(d),.rst(rst),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_adff");
+		$dumpvars(0,tb_adff);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_adffe.v

@@ -0,0 +1,58 @@
+`timescale 1ns/1ns 
+module tb_adffe();
+	reg clk = 0;
+	reg rst = 0;
+	reg d = 0;
+	reg en = 0;
+	wire q;
+
+	adffe uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_adffe");
+		$dumpvars(0,tb_adffe);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		en = 1;
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_adlatch.v

@@ -0,0 +1,70 @@
+`timescale 1ns/1ns 
+module tb_adlatch();
+	reg clk = 0;
+	reg rst = 0;
+	reg en = 0;
+	reg d = 0;
+	wire q;
+
+	adlatch uut(.d(d),.rst(rst),.en(en),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_adlatch");
+		$dumpvars(0,tb_adlatch);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		en = 1;
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_aldff.v

@@ -0,0 +1,73 @@
+`timescale 1ns/1ns 
+module tb_aldff();
+	reg clk = 0;
+	reg aload = 0;
+	reg [0:3] d  = 4'b0000;
+	reg [0:3] ad = 4'b1010;
+	wire [0:3] q;
+
+	aldff uut(.clk(clk),.d(d),.ad(ad),.aload(aload),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_aldff");
+		$dumpvars(0,tb_aldff);
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		aload = 1;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		aload = 0;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		aload = 1;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		aload = 0;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_aldffe.v

@@ -0,0 +1,75 @@
+`timescale 1ns/1ns 
+module tb_aldffe();
+	reg clk = 0;
+	reg aload = 0;
+	reg [0:3] d  = 4'b0000;
+	reg [0:3] ad = 4'b1010;
+	reg en = 0;
+	wire [0:3] q;
+
+	aldffe uut(.clk(clk),.d(d),.ad(ad),.aload(aload),.en(en),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_aldffe");
+		$dumpvars(0,tb_aldffe);
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		aload = 1;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		aload = 0;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		en = 1;
+		aload = 1;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		aload = 0;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		d = 4'b1100;
+		#10
+		d = 4'b0011;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_dff.v

@@ -0,0 +1,47 @@
+`timescale 1ns/1ns 
+module tb_dff();
+	reg clk = 0;
+	reg d = 0;
+	wire q;
+
+	dff uut(.clk(clk),.d(d),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_dff");
+		$dumpvars(0,tb_dff);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_dffe.v

@@ -0,0 +1,42 @@
+`timescale 1ns/1ns 
+module tb_dffe();
+	reg clk = 0;
+	reg en = 0;
+	reg d = 0;
+	wire q;
+
+	dffe uut(.clk(clk),.d(d),.en(en),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_dffe");
+		$dumpvars(0,tb_dffe);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		en = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_dffsr.v

@@ -0,0 +1,69 @@
+`timescale 1ns/1ns 
+module tb_dffsr();
+	reg clk = 0;
+	reg d = 0;
+	reg set = 0;
+	reg clr = 0;
+	wire q;
+
+	dffsr uut(.d(d),.clk(clk),.set(set),.clr(clr),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_dffsr");
+		$dumpvars(0,tb_dffsr);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		clr = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		clr = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		set = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		set = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_dlatch.v

@@ -0,0 +1,50 @@
+`timescale 1ns/1ns 
+module tb_dlatch();
+	reg clk = 0;
+	reg en = 0;
+	reg d = 0;
+	wire q;
+
+	dlatch uut(.d(d),.en(en),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_dlatch");
+		$dumpvars(0,tb_dlatch);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		en = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_sdff.v

@@ -0,0 +1,48 @@
+`timescale 1ns/1ns 
+module tb_sdff();
+	reg clk = 0;
+	reg rst = 0;
+	reg d = 0;
+	wire q;
+
+	sdff uut(.clk(clk),.d(d),.rst(rst),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_sdff");
+		$dumpvars(0,tb_sdff);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_sdffce.v

@@ -0,0 +1,79 @@
+`timescale 1ns/1ns 
+module tb_sdffce();
+	reg clk = 0;
+	reg rst = 0;
+	reg d = 0;
+	reg en = 0;
+	wire q;
+
+	sdffce uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_sdffce");
+		$dumpvars(0,tb_sdffce);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		en = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule

tests/sim/tb/tb_sdffe.v

@@ -0,0 +1,70 @@
+`timescale 1ns/1ns 
+module tb_sdffe();
+	reg clk = 0;
+	reg rst = 0;
+	reg d = 0;
+	reg en = 0;
+	wire q;
+
+	sdffe uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q));
+
+	always
+		#(5) clk <= !clk;
+
+	initial
+	begin
+		$dumpfile("tb_sdffe");
+		$dumpvars(0,tb_sdffe);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		en = 1;
+		rst = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		rst = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule