mirror of https://github.com/YosysHQ/yosys.git
xilinx: Use `memory_libmap` pass.
This commit is contained in:
Marcelina Kościelnicka
parent
e4d811561c
commit
3b2f95953c
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@ -1,2 +0,0 @@
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brams_init.mk
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brams_init_*.vh
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@ -2,45 +2,37 @@
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OBJS += techlibs/xilinx/synth_xilinx.o
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OBJS += techlibs/xilinx/xilinx_dffopt.o
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GENFILES += techlibs/xilinx/brams_init_36.vh
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GENFILES += techlibs/xilinx/brams_init_32.vh
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GENFILES += techlibs/xilinx/brams_init_18.vh
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GENFILES += techlibs/xilinx/brams_init_16.vh
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GENFILES += techlibs/xilinx/brams_init_9.vh
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GENFILES += techlibs/xilinx/brams_init_8.vh
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EXTRA_OBJS += techlibs/xilinx/brams_init.mk
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.SECONDARY: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py
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$(Q) mkdir -p techlibs/xilinx
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$(P) $(PYTHON_EXECUTABLE) $<
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$(Q) touch $@
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techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_32.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_18.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_16.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_9.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc2v_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc2v_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sa_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut4_lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut6_lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcv.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcv_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xc5v.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xcu.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_xc5v_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcv.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcv_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_defs.vh))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc2v.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc2v_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc3sda.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc3sda_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc4v.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc4v_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc5v_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xc6v_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_xcu_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/urams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/urams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
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@ -54,11 +46,3 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_9.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_8.vh))
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@ -0,0 +1,561 @@
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`define PARAMS_INIT_9 \
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.INIT_00(slice_init('h00)), \
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.INIT_01(slice_init('h01)), \
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.INIT_02(slice_init('h02)), \
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.INIT_03(slice_init('h03)), \
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.INIT_04(slice_init('h04)), \
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.INIT_05(slice_init('h05)), \
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.INIT_06(slice_init('h06)), \
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.INIT_07(slice_init('h07)), \
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.INIT_08(slice_init('h08)), \
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.INIT_09(slice_init('h09)), \
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.INIT_0A(slice_init('h0a)), \
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.INIT_0B(slice_init('h0b)), \
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.INIT_0C(slice_init('h0c)), \
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.INIT_0D(slice_init('h0d)), \
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.INIT_0E(slice_init('h0e)), \
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.INIT_0F(slice_init('h0f)), \
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.INIT_10(slice_init('h10)), \
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.INIT_11(slice_init('h11)), \
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.INIT_12(slice_init('h12)), \
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.INIT_13(slice_init('h13)), \
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.INIT_14(slice_init('h14)), \
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.INIT_15(slice_init('h15)), \
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.INIT_16(slice_init('h16)), \
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.INIT_17(slice_init('h17)), \
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.INIT_18(slice_init('h18)), \
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.INIT_19(slice_init('h19)), \
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.INIT_1A(slice_init('h1a)), \
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.INIT_1B(slice_init('h1b)), \
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.INIT_1C(slice_init('h1c)), \
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.INIT_1D(slice_init('h1d)), \
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.INIT_1E(slice_init('h1e)), \
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.INIT_1F(slice_init('h1f)),
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`define PARAMS_INITP_9 \
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.INITP_00(slice_initp('h00)), \
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.INITP_01(slice_initp('h01)), \
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.INITP_02(slice_initp('h02)), \
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.INITP_03(slice_initp('h03)),
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`define PARAMS_INIT_18 \
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.INIT_00(slice_init('h00)), \
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.INIT_01(slice_init('h01)), \
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.INIT_02(slice_init('h02)), \
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.INIT_03(slice_init('h03)), \
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.INIT_04(slice_init('h04)), \
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.INIT_05(slice_init('h05)), \
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.INIT_06(slice_init('h06)), \
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.INIT_07(slice_init('h07)), \
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.INIT_08(slice_init('h08)), \
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.INIT_09(slice_init('h09)), \
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.INIT_0A(slice_init('h0a)), \
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.INIT_0B(slice_init('h0b)), \
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.INIT_0C(slice_init('h0c)), \
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.INIT_0D(slice_init('h0d)), \
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.INIT_0E(slice_init('h0e)), \
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.INIT_0F(slice_init('h0f)), \
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.INIT_10(slice_init('h10)), \
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.INIT_11(slice_init('h11)), \
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.INIT_12(slice_init('h12)), \
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.INIT_13(slice_init('h13)), \
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.INIT_14(slice_init('h14)), \
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.INIT_15(slice_init('h15)), \
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.INIT_16(slice_init('h16)), \
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.INIT_17(slice_init('h17)), \
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.INIT_18(slice_init('h18)), \
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.INIT_19(slice_init('h19)), \
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.INIT_1A(slice_init('h1a)), \
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.INIT_1B(slice_init('h1b)), \
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.INIT_1C(slice_init('h1c)), \
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.INIT_1D(slice_init('h1d)), \
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.INIT_1E(slice_init('h1e)), \
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.INIT_1F(slice_init('h1f)), \
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.INIT_20(slice_init('h20)), \
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||||
.INIT_21(slice_init('h21)), \
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||||
.INIT_22(slice_init('h22)), \
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||||
.INIT_23(slice_init('h23)), \
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||||
.INIT_24(slice_init('h24)), \
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||||
.INIT_25(slice_init('h25)), \
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||||
.INIT_26(slice_init('h26)), \
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||||
.INIT_27(slice_init('h27)), \
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||||
.INIT_28(slice_init('h28)), \
|
||||
.INIT_29(slice_init('h29)), \
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||||
.INIT_2A(slice_init('h2a)), \
|
||||
.INIT_2B(slice_init('h2b)), \
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||||
.INIT_2C(slice_init('h2c)), \
|
||||
.INIT_2D(slice_init('h2d)), \
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||||
.INIT_2E(slice_init('h2e)), \
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||||
.INIT_2F(slice_init('h2f)), \
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||||
.INIT_30(slice_init('h30)), \
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||||
.INIT_31(slice_init('h31)), \
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||||
.INIT_32(slice_init('h32)), \
|
||||
.INIT_33(slice_init('h33)), \
|
||||
.INIT_34(slice_init('h34)), \
|
||||
.INIT_35(slice_init('h35)), \
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||||
.INIT_36(slice_init('h36)), \
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||||
.INIT_37(slice_init('h37)), \
|
||||
.INIT_38(slice_init('h38)), \
|
||||
.INIT_39(slice_init('h39)), \
|
||||
.INIT_3A(slice_init('h3a)), \
|
||||
.INIT_3B(slice_init('h3b)), \
|
||||
.INIT_3C(slice_init('h3c)), \
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||||
.INIT_3D(slice_init('h3d)), \
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.INIT_3E(slice_init('h3e)), \
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.INIT_3F(slice_init('h3f)),
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`define PARAMS_INIT_18_U \
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.INIT_00(slice_init('h40)), \
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.INIT_01(slice_init('h41)), \
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.INIT_02(slice_init('h42)), \
|
||||
.INIT_03(slice_init('h43)), \
|
||||
.INIT_04(slice_init('h44)), \
|
||||
.INIT_05(slice_init('h45)), \
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||||
.INIT_06(slice_init('h46)), \
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.INIT_07(slice_init('h47)), \
|
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.INIT_08(slice_init('h48)), \
|
||||
.INIT_09(slice_init('h49)), \
|
||||
.INIT_0A(slice_init('h4a)), \
|
||||
.INIT_0B(slice_init('h4b)), \
|
||||
.INIT_0C(slice_init('h4c)), \
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||||
.INIT_0D(slice_init('h4d)), \
|
||||
.INIT_0E(slice_init('h4e)), \
|
||||
.INIT_0F(slice_init('h4f)), \
|
||||
.INIT_10(slice_init('h50)), \
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||||
.INIT_11(slice_init('h51)), \
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||||
.INIT_12(slice_init('h52)), \
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||||
.INIT_13(slice_init('h53)), \
|
||||
.INIT_14(slice_init('h54)), \
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||||
.INIT_15(slice_init('h55)), \
|
||||
.INIT_16(slice_init('h56)), \
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||||
.INIT_17(slice_init('h57)), \
|
||||
.INIT_18(slice_init('h58)), \
|
||||
.INIT_19(slice_init('h59)), \
|
||||
.INIT_1A(slice_init('h5a)), \
|
||||
.INIT_1B(slice_init('h5b)), \
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||||
.INIT_1C(slice_init('h5c)), \
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||||
.INIT_1D(slice_init('h5d)), \
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||||
.INIT_1E(slice_init('h5e)), \
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.INIT_1F(slice_init('h5f)), \
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.INIT_20(slice_init('h60)), \
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||||
.INIT_21(slice_init('h61)), \
|
||||
.INIT_22(slice_init('h62)), \
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||||
.INIT_23(slice_init('h63)), \
|
||||
.INIT_24(slice_init('h64)), \
|
||||
.INIT_25(slice_init('h65)), \
|
||||
.INIT_26(slice_init('h66)), \
|
||||
.INIT_27(slice_init('h67)), \
|
||||
.INIT_28(slice_init('h68)), \
|
||||
.INIT_29(slice_init('h69)), \
|
||||
.INIT_2A(slice_init('h6a)), \
|
||||
.INIT_2B(slice_init('h6b)), \
|
||||
.INIT_2C(slice_init('h6c)), \
|
||||
.INIT_2D(slice_init('h6d)), \
|
||||
.INIT_2E(slice_init('h6e)), \
|
||||
.INIT_2F(slice_init('h6f)), \
|
||||
.INIT_30(slice_init('h70)), \
|
||||
.INIT_31(slice_init('h71)), \
|
||||
.INIT_32(slice_init('h72)), \
|
||||
.INIT_33(slice_init('h73)), \
|
||||
.INIT_34(slice_init('h74)), \
|
||||
.INIT_35(slice_init('h75)), \
|
||||
.INIT_36(slice_init('h76)), \
|
||||
.INIT_37(slice_init('h77)), \
|
||||
.INIT_38(slice_init('h78)), \
|
||||
.INIT_39(slice_init('h79)), \
|
||||
.INIT_3A(slice_init('h7a)), \
|
||||
.INIT_3B(slice_init('h7b)), \
|
||||
.INIT_3C(slice_init('h7c)), \
|
||||
.INIT_3D(slice_init('h7d)), \
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.INIT_3E(slice_init('h7e)), \
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.INIT_3F(slice_init('h7f)),
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`define PARAMS_INITP_18 \
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.INITP_00(slice_initp('h00)), \
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.INITP_01(slice_initp('h01)), \
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||||
.INITP_02(slice_initp('h02)), \
|
||||
.INITP_03(slice_initp('h03)), \
|
||||
.INITP_04(slice_initp('h04)), \
|
||||
.INITP_05(slice_initp('h05)), \
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||||
.INITP_06(slice_initp('h06)), \
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||||
.INITP_07(slice_initp('h07)),
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`define PARAMS_INIT_36 \
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||||
.INIT_00(slice_init('h00)), \
|
||||
.INIT_01(slice_init('h01)), \
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||||
.INIT_02(slice_init('h02)), \
|
||||
.INIT_03(slice_init('h03)), \
|
||||
.INIT_04(slice_init('h04)), \
|
||||
.INIT_05(slice_init('h05)), \
|
||||
.INIT_06(slice_init('h06)), \
|
||||
.INIT_07(slice_init('h07)), \
|
||||
.INIT_08(slice_init('h08)), \
|
||||
.INIT_09(slice_init('h09)), \
|
||||
.INIT_0A(slice_init('h0a)), \
|
||||
.INIT_0B(slice_init('h0b)), \
|
||||
.INIT_0C(slice_init('h0c)), \
|
||||
.INIT_0D(slice_init('h0d)), \
|
||||
.INIT_0E(slice_init('h0e)), \
|
||||
.INIT_0F(slice_init('h0f)), \
|
||||
.INIT_10(slice_init('h10)), \
|
||||
.INIT_11(slice_init('h11)), \
|
||||
.INIT_12(slice_init('h12)), \
|
||||
.INIT_13(slice_init('h13)), \
|
||||
.INIT_14(slice_init('h14)), \
|
||||
.INIT_15(slice_init('h15)), \
|
||||
.INIT_16(slice_init('h16)), \
|
||||
.INIT_17(slice_init('h17)), \
|
||||
.INIT_18(slice_init('h18)), \
|
||||
.INIT_19(slice_init('h19)), \
|
||||
.INIT_1A(slice_init('h1a)), \
|
||||
.INIT_1B(slice_init('h1b)), \
|
||||
.INIT_1C(slice_init('h1c)), \
|
||||
.INIT_1D(slice_init('h1d)), \
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||||
.INIT_1E(slice_init('h1e)), \
|
||||
.INIT_1F(slice_init('h1f)), \
|
||||
.INIT_20(slice_init('h20)), \
|
||||
.INIT_21(slice_init('h21)), \
|
||||
.INIT_22(slice_init('h22)), \
|
||||
.INIT_23(slice_init('h23)), \
|
||||
.INIT_24(slice_init('h24)), \
|
||||
.INIT_25(slice_init('h25)), \
|
||||
.INIT_26(slice_init('h26)), \
|
||||
.INIT_27(slice_init('h27)), \
|
||||
.INIT_28(slice_init('h28)), \
|
||||
.INIT_29(slice_init('h29)), \
|
||||
.INIT_2A(slice_init('h2a)), \
|
||||
.INIT_2B(slice_init('h2b)), \
|
||||
.INIT_2C(slice_init('h2c)), \
|
||||
.INIT_2D(slice_init('h2d)), \
|
||||
.INIT_2E(slice_init('h2e)), \
|
||||
.INIT_2F(slice_init('h2f)), \
|
||||
.INIT_30(slice_init('h30)), \
|
||||
.INIT_31(slice_init('h31)), \
|
||||
.INIT_32(slice_init('h32)), \
|
||||
.INIT_33(slice_init('h33)), \
|
||||
.INIT_34(slice_init('h34)), \
|
||||
.INIT_35(slice_init('h35)), \
|
||||
.INIT_36(slice_init('h36)), \
|
||||
.INIT_37(slice_init('h37)), \
|
||||
.INIT_38(slice_init('h38)), \
|
||||
.INIT_39(slice_init('h39)), \
|
||||
.INIT_3A(slice_init('h3a)), \
|
||||
.INIT_3B(slice_init('h3b)), \
|
||||
.INIT_3C(slice_init('h3c)), \
|
||||
.INIT_3D(slice_init('h3d)), \
|
||||
.INIT_3E(slice_init('h3e)), \
|
||||
.INIT_3F(slice_init('h3f)), \
|
||||
.INIT_40(slice_init('h40)), \
|
||||
.INIT_41(slice_init('h41)), \
|
||||
.INIT_42(slice_init('h42)), \
|
||||
.INIT_43(slice_init('h43)), \
|
||||
.INIT_44(slice_init('h44)), \
|
||||
.INIT_45(slice_init('h45)), \
|
||||
.INIT_46(slice_init('h46)), \
|
||||
.INIT_47(slice_init('h47)), \
|
||||
.INIT_48(slice_init('h48)), \
|
||||
.INIT_49(slice_init('h49)), \
|
||||
.INIT_4A(slice_init('h4a)), \
|
||||
.INIT_4B(slice_init('h4b)), \
|
||||
.INIT_4C(slice_init('h4c)), \
|
||||
.INIT_4D(slice_init('h4d)), \
|
||||
.INIT_4E(slice_init('h4e)), \
|
||||
.INIT_4F(slice_init('h4f)), \
|
||||
.INIT_50(slice_init('h50)), \
|
||||
.INIT_51(slice_init('h51)), \
|
||||
.INIT_52(slice_init('h52)), \
|
||||
.INIT_53(slice_init('h53)), \
|
||||
.INIT_54(slice_init('h54)), \
|
||||
.INIT_55(slice_init('h55)), \
|
||||
.INIT_56(slice_init('h56)), \
|
||||
.INIT_57(slice_init('h57)), \
|
||||
.INIT_58(slice_init('h58)), \
|
||||
.INIT_59(slice_init('h59)), \
|
||||
.INIT_5A(slice_init('h5a)), \
|
||||
.INIT_5B(slice_init('h5b)), \
|
||||
.INIT_5C(slice_init('h5c)), \
|
||||
.INIT_5D(slice_init('h5d)), \
|
||||
.INIT_5E(slice_init('h5e)), \
|
||||
.INIT_5F(slice_init('h5f)), \
|
||||
.INIT_60(slice_init('h60)), \
|
||||
.INIT_61(slice_init('h61)), \
|
||||
.INIT_62(slice_init('h62)), \
|
||||
.INIT_63(slice_init('h63)), \
|
||||
.INIT_64(slice_init('h64)), \
|
||||
.INIT_65(slice_init('h65)), \
|
||||
.INIT_66(slice_init('h66)), \
|
||||
.INIT_67(slice_init('h67)), \
|
||||
.INIT_68(slice_init('h68)), \
|
||||
.INIT_69(slice_init('h69)), \
|
||||
.INIT_6A(slice_init('h6a)), \
|
||||
.INIT_6B(slice_init('h6b)), \
|
||||
.INIT_6C(slice_init('h6c)), \
|
||||
.INIT_6D(slice_init('h6d)), \
|
||||
.INIT_6E(slice_init('h6e)), \
|
||||
.INIT_6F(slice_init('h6f)), \
|
||||
.INIT_70(slice_init('h70)), \
|
||||
.INIT_71(slice_init('h71)), \
|
||||
.INIT_72(slice_init('h72)), \
|
||||
.INIT_73(slice_init('h73)), \
|
||||
.INIT_74(slice_init('h74)), \
|
||||
.INIT_75(slice_init('h75)), \
|
||||
.INIT_76(slice_init('h76)), \
|
||||
.INIT_77(slice_init('h77)), \
|
||||
.INIT_78(slice_init('h78)), \
|
||||
.INIT_79(slice_init('h79)), \
|
||||
.INIT_7A(slice_init('h7a)), \
|
||||
.INIT_7B(slice_init('h7b)), \
|
||||
.INIT_7C(slice_init('h7c)), \
|
||||
.INIT_7D(slice_init('h7d)), \
|
||||
.INIT_7E(slice_init('h7e)), \
|
||||
.INIT_7F(slice_init('h7f)),
|
||||
|
||||
`define PARAMS_INIT_36_U \
|
||||
.INIT_00(slice_init('h80)), \
|
||||
.INIT_01(slice_init('h81)), \
|
||||
.INIT_02(slice_init('h82)), \
|
||||
.INIT_03(slice_init('h83)), \
|
||||
.INIT_04(slice_init('h84)), \
|
||||
.INIT_05(slice_init('h85)), \
|
||||
.INIT_06(slice_init('h86)), \
|
||||
.INIT_07(slice_init('h87)), \
|
||||
.INIT_08(slice_init('h88)), \
|
||||
.INIT_09(slice_init('h89)), \
|
||||
.INIT_0A(slice_init('h8a)), \
|
||||
.INIT_0B(slice_init('h8b)), \
|
||||
.INIT_0C(slice_init('h8c)), \
|
||||
.INIT_0D(slice_init('h8d)), \
|
||||
.INIT_0E(slice_init('h8e)), \
|
||||
.INIT_0F(slice_init('h8f)), \
|
||||
.INIT_10(slice_init('h90)), \
|
||||
.INIT_11(slice_init('h91)), \
|
||||
.INIT_12(slice_init('h92)), \
|
||||
.INIT_13(slice_init('h93)), \
|
||||
.INIT_14(slice_init('h94)), \
|
||||
.INIT_15(slice_init('h95)), \
|
||||
.INIT_16(slice_init('h96)), \
|
||||
.INIT_17(slice_init('h97)), \
|
||||
.INIT_18(slice_init('h98)), \
|
||||
.INIT_19(slice_init('h99)), \
|
||||
.INIT_1A(slice_init('h9a)), \
|
||||
.INIT_1B(slice_init('h9b)), \
|
||||
.INIT_1C(slice_init('h9c)), \
|
||||
.INIT_1D(slice_init('h9d)), \
|
||||
.INIT_1E(slice_init('h9e)), \
|
||||
.INIT_1F(slice_init('h9f)), \
|
||||
.INIT_20(slice_init('ha0)), \
|
||||
.INIT_21(slice_init('ha1)), \
|
||||
.INIT_22(slice_init('ha2)), \
|
||||
.INIT_23(slice_init('ha3)), \
|
||||
.INIT_24(slice_init('ha4)), \
|
||||
.INIT_25(slice_init('ha5)), \
|
||||
.INIT_26(slice_init('ha6)), \
|
||||
.INIT_27(slice_init('ha7)), \
|
||||
.INIT_28(slice_init('ha8)), \
|
||||
.INIT_29(slice_init('ha9)), \
|
||||
.INIT_2A(slice_init('haa)), \
|
||||
.INIT_2B(slice_init('hab)), \
|
||||
.INIT_2C(slice_init('hac)), \
|
||||
.INIT_2D(slice_init('had)), \
|
||||
.INIT_2E(slice_init('hae)), \
|
||||
.INIT_2F(slice_init('haf)), \
|
||||
.INIT_30(slice_init('hb0)), \
|
||||
.INIT_31(slice_init('hb1)), \
|
||||
.INIT_32(slice_init('hb2)), \
|
||||
.INIT_33(slice_init('hb3)), \
|
||||
.INIT_34(slice_init('hb4)), \
|
||||
.INIT_35(slice_init('hb5)), \
|
||||
.INIT_36(slice_init('hb6)), \
|
||||
.INIT_37(slice_init('hb7)), \
|
||||
.INIT_38(slice_init('hb8)), \
|
||||
.INIT_39(slice_init('hb9)), \
|
||||
.INIT_3A(slice_init('hba)), \
|
||||
.INIT_3B(slice_init('hbb)), \
|
||||
.INIT_3C(slice_init('hbc)), \
|
||||
.INIT_3D(slice_init('hbd)), \
|
||||
.INIT_3E(slice_init('hbe)), \
|
||||
.INIT_3F(slice_init('hbf)), \
|
||||
.INIT_40(slice_init('hc0)), \
|
||||
.INIT_41(slice_init('hc1)), \
|
||||
.INIT_42(slice_init('hc2)), \
|
||||
.INIT_43(slice_init('hc3)), \
|
||||
.INIT_44(slice_init('hc4)), \
|
||||
.INIT_45(slice_init('hc5)), \
|
||||
.INIT_46(slice_init('hc6)), \
|
||||
.INIT_47(slice_init('hc7)), \
|
||||
.INIT_48(slice_init('hc8)), \
|
||||
.INIT_49(slice_init('hc9)), \
|
||||
.INIT_4A(slice_init('hca)), \
|
||||
.INIT_4B(slice_init('hcb)), \
|
||||
.INIT_4C(slice_init('hcc)), \
|
||||
.INIT_4D(slice_init('hcd)), \
|
||||
.INIT_4E(slice_init('hce)), \
|
||||
.INIT_4F(slice_init('hcf)), \
|
||||
.INIT_50(slice_init('hd0)), \
|
||||
.INIT_51(slice_init('hd1)), \
|
||||
.INIT_52(slice_init('hd2)), \
|
||||
.INIT_53(slice_init('hd3)), \
|
||||
.INIT_54(slice_init('hd4)), \
|
||||
.INIT_55(slice_init('hd5)), \
|
||||
.INIT_56(slice_init('hd6)), \
|
||||
.INIT_57(slice_init('hd7)), \
|
||||
.INIT_58(slice_init('hd8)), \
|
||||
.INIT_59(slice_init('hd9)), \
|
||||
.INIT_5A(slice_init('hda)), \
|
||||
.INIT_5B(slice_init('hdb)), \
|
||||
.INIT_5C(slice_init('hdc)), \
|
||||
.INIT_5D(slice_init('hdd)), \
|
||||
.INIT_5E(slice_init('hde)), \
|
||||
.INIT_5F(slice_init('hdf)), \
|
||||
.INIT_60(slice_init('he0)), \
|
||||
.INIT_61(slice_init('he1)), \
|
||||
.INIT_62(slice_init('he2)), \
|
||||
.INIT_63(slice_init('he3)), \
|
||||
.INIT_64(slice_init('he4)), \
|
||||
.INIT_65(slice_init('he5)), \
|
||||
.INIT_66(slice_init('he6)), \
|
||||
.INIT_67(slice_init('he7)), \
|
||||
.INIT_68(slice_init('he8)), \
|
||||
.INIT_69(slice_init('he9)), \
|
||||
.INIT_6A(slice_init('hea)), \
|
||||
.INIT_6B(slice_init('heb)), \
|
||||
.INIT_6C(slice_init('hec)), \
|
||||
.INIT_6D(slice_init('hed)), \
|
||||
.INIT_6E(slice_init('hee)), \
|
||||
.INIT_6F(slice_init('hef)), \
|
||||
.INIT_70(slice_init('hf0)), \
|
||||
.INIT_71(slice_init('hf1)), \
|
||||
.INIT_72(slice_init('hf2)), \
|
||||
.INIT_73(slice_init('hf3)), \
|
||||
.INIT_74(slice_init('hf4)), \
|
||||
.INIT_75(slice_init('hf5)), \
|
||||
.INIT_76(slice_init('hf6)), \
|
||||
.INIT_77(slice_init('hf7)), \
|
||||
.INIT_78(slice_init('hf8)), \
|
||||
.INIT_79(slice_init('hf9)), \
|
||||
.INIT_7A(slice_init('hfa)), \
|
||||
.INIT_7B(slice_init('hfb)), \
|
||||
.INIT_7C(slice_init('hfc)), \
|
||||
.INIT_7D(slice_init('hfd)), \
|
||||
.INIT_7E(slice_init('hfe)), \
|
||||
.INIT_7F(slice_init('hff)),
|
||||
|
||||
`define PARAMS_INITP_36 \
|
||||
.INITP_00(slice_initp('h00)), \
|
||||
.INITP_01(slice_initp('h01)), \
|
||||
.INITP_02(slice_initp('h02)), \
|
||||
.INITP_03(slice_initp('h03)), \
|
||||
.INITP_04(slice_initp('h04)), \
|
||||
.INITP_05(slice_initp('h05)), \
|
||||
.INITP_06(slice_initp('h06)), \
|
||||
.INITP_07(slice_initp('h07)), \
|
||||
.INITP_08(slice_initp('h08)), \
|
||||
.INITP_09(slice_initp('h09)), \
|
||||
.INITP_0A(slice_initp('h0a)), \
|
||||
.INITP_0B(slice_initp('h0b)), \
|
||||
.INITP_0C(slice_initp('h0c)), \
|
||||
.INITP_0D(slice_initp('h0d)), \
|
||||
.INITP_0E(slice_initp('h0e)), \
|
||||
.INITP_0F(slice_initp('h0f)),
|
||||
|
||||
`define MAKE_DO(do, dop, rdata) \
|
||||
wire [63:0] do; \
|
||||
wire [7:0] dop; \
|
||||
assign rdata = { \
|
||||
dop[7], \
|
||||
do[63:56], \
|
||||
dop[6], \
|
||||
do[55:48], \
|
||||
dop[5], \
|
||||
do[47:40], \
|
||||
dop[4], \
|
||||
do[39:32], \
|
||||
dop[3], \
|
||||
do[31:24], \
|
||||
dop[2], \
|
||||
do[23:16], \
|
||||
dop[1], \
|
||||
do[15:8], \
|
||||
dop[0], \
|
||||
do[7:0] \
|
||||
};
|
||||
|
||||
`define MAKE_DI(di, dip, wdata) \
|
||||
wire [63:0] di; \
|
||||
wire [7:0] dip; \
|
||||
assign { \
|
||||
dip[7], \
|
||||
di[63:56], \
|
||||
dip[6], \
|
||||
di[55:48], \
|
||||
dip[5], \
|
||||
di[47:40], \
|
||||
dip[4], \
|
||||
di[39:32], \
|
||||
dip[3], \
|
||||
di[31:24], \
|
||||
dip[2], \
|
||||
di[23:16], \
|
||||
dip[1], \
|
||||
di[15:8], \
|
||||
dip[0], \
|
||||
di[7:0] \
|
||||
} = wdata;
|
||||
|
||||
function [71:0] ival;
|
||||
input integer width;
|
||||
input [71:0] val;
|
||||
if (width == 72)
|
||||
ival = {
|
||||
val[71],
|
||||
val[62],
|
||||
val[53],
|
||||
val[44],
|
||||
val[35],
|
||||
val[26],
|
||||
val[17],
|
||||
val[8],
|
||||
val[70:63],
|
||||
val[61:54],
|
||||
val[52:45],
|
||||
val[43:36],
|
||||
val[34:27],
|
||||
val[25:18],
|
||||
val[16:9],
|
||||
val[7:0]
|
||||
};
|
||||
else if (width == 36)
|
||||
ival = {
|
||||
val[35],
|
||||
val[26],
|
||||
val[17],
|
||||
val[8],
|
||||
val[34:27],
|
||||
val[25:18],
|
||||
val[16:9],
|
||||
val[7:0]
|
||||
};
|
||||
else if (width == 18)
|
||||
ival = {
|
||||
val[17],
|
||||
val[8],
|
||||
val[16:9],
|
||||
val[7:0]
|
||||
};
|
||||
else
|
||||
ival = val;
|
||||
endfunction
|
||||
|
||||
function [255:0] slice_init;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < 32; i = i + 1)
|
||||
slice_init[i*8+:8] = INIT[(idx * 32 + i)*9+:8];
|
||||
endfunction
|
||||
|
||||
function [255:0] slice_initp;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < 256; i = i + 1)
|
||||
slice_initp[i] = INIT[(idx * 256 + i)*9+8];
|
||||
endfunction
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
with open("techlibs/xilinx/brams_init_9.vh", "w") as f:
|
||||
for i in range(4):
|
||||
init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
|
||||
for k in range(4, 256, 4):
|
||||
init_snippets[k] = "\n " + init_snippets[k]
|
||||
print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
|
||||
for i in range(32):
|
||||
init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
|
||||
for k in range(4, 32, 4):
|
||||
init_snippets[k] = "\n " + init_snippets[k]
|
||||
print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
|
||||
|
||||
with open("techlibs/xilinx/brams_init_18.vh", "w") as f:
|
||||
for i in range(8):
|
||||
init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
|
||||
for k in range(4, 256, 4):
|
||||
init_snippets[k] = "\n " + init_snippets[k]
|
||||
print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
|
||||
for i in range(64):
|
||||
init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
|
||||
for k in range(4, 32, 4):
|
||||
init_snippets[k] = "\n " + init_snippets[k]
|
||||
print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
|
||||
|
||||
with open("techlibs/xilinx/brams_init_36.vh", "w") as f:
|
||||
for i in range(16):
|
||||
init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
|
||||
for k in range(4, 256, 4):
|
||||
init_snippets[k] = "\n " + init_snippets[k]
|
||||
print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
|
||||
for i in range(128):
|
||||
init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
|
||||
for k in range(4, 32, 4):
|
||||
init_snippets[k] = "\n " + init_snippets[k]
|
||||
print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
|
||||
|
||||
with open("techlibs/xilinx/brams_init_8.vh", "w") as f:
|
||||
for i in range(32):
|
||||
print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
|
||||
|
||||
with open("techlibs/xilinx/brams_init_16.vh", "w") as f:
|
||||
for i in range(64):
|
||||
print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
|
||||
|
||||
with open("techlibs/xilinx/brams_init_32.vh", "w") as f:
|
||||
for i in range(128):
|
||||
print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
# Block RAMs for Virtex 2, Spartan 3, Spartan 3E, Spartan 3A(N)
|
||||
# The corresponding mapping file is brams_xc2v_map.v
|
||||
|
||||
ram block $__XILINX_BLOCKRAM_ {
|
||||
abits 14;
|
||||
widths 1 2 4 9 18 36 per_port;
|
||||
ifdef HAS_BE {
|
||||
option "USE_BE" 1 byte 9;
|
||||
}
|
||||
cost 129;
|
||||
init any;
|
||||
port srsw "A" "B" {
|
||||
option "USE_BE" 0 width tied;
|
||||
ifdef HAS_BE {
|
||||
option "USE_BE" 1 width tied 9 18 36;
|
||||
}
|
||||
clock posedge;
|
||||
clken;
|
||||
rdsrst any gated_clken;
|
||||
rdinit any;
|
||||
portoption "WRITE_MODE" "NO_CHANGE" {
|
||||
rdwr no_change;
|
||||
}
|
||||
portoption "WRITE_MODE" "WRITE_FIRST" {
|
||||
rdwr new_only;
|
||||
}
|
||||
portoption "WRITE_MODE" "READ_FIRST" {
|
||||
rdwr old;
|
||||
wrtrans all old;
|
||||
}
|
||||
optional;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,532 @@
|
|||
module $__XILINX_BLOCKRAM_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_USE_BE = 0;
|
||||
|
||||
parameter PORT_A_WIDTH = 1;
|
||||
parameter PORT_A_WR_EN_WIDTH = 1;
|
||||
parameter PORT_A_USED = 1;
|
||||
parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_A_RD_INIT_VALUE = 0;
|
||||
parameter PORT_A_RD_SRST_VALUE = 0;
|
||||
|
||||
parameter PORT_B_WIDTH = 1;
|
||||
parameter PORT_B_WR_EN_WIDTH = 1;
|
||||
parameter PORT_B_USED = 0;
|
||||
parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_B_RD_INIT_VALUE = 0;
|
||||
parameter PORT_B_RD_SRST_VALUE = 0;
|
||||
|
||||
input PORT_A_CLK;
|
||||
input PORT_A_CLK_EN;
|
||||
input [13:0] PORT_A_ADDR;
|
||||
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
|
||||
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
|
||||
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
|
||||
input PORT_A_RD_SRST;
|
||||
|
||||
input PORT_B_CLK;
|
||||
input PORT_B_CLK_EN;
|
||||
input [13:0] PORT_B_ADDR;
|
||||
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
|
||||
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
|
||||
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
|
||||
input PORT_B_RD_SRST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_DP \
|
||||
`PARAMS_INIT_18 \
|
||||
.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
|
||||
.SRVAL_A(SRVAL_A), \
|
||||
.SRVAL_B(SRVAL_B), \
|
||||
.INIT_A(INIT_A), \
|
||||
.INIT_B(INIT_B),
|
||||
|
||||
`define PARAMS_DP_SWAP \
|
||||
`PARAMS_INIT_18 \
|
||||
.WRITE_MODE_A(PORT_B_OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(PORT_A_OPTION_WRITE_MODE), \
|
||||
.SRVAL_A(SRVAL_B), \
|
||||
.SRVAL_B(SRVAL_A), \
|
||||
.INIT_A(INIT_B), \
|
||||
.INIT_B(INIT_A),
|
||||
|
||||
`define PARAMS_SP \
|
||||
`PARAMS_INIT_18 \
|
||||
.WRITE_MODE(PORT_A_OPTION_WRITE_MODE), \
|
||||
.SRVAL(SRVAL_A), \
|
||||
.INIT(INIT_A),
|
||||
|
||||
`define PORTS_DP(addr_slice_a, addr_slice_b) \
|
||||
.CLKA(PORT_A_CLK), \
|
||||
.ENA(PORT_A_CLK_EN), \
|
||||
.WEA(PORT_A_WR_EN), \
|
||||
.SSRA(PORT_A_RD_SRST), \
|
||||
.ADDRA(PORT_A_ADDR addr_slice_a), \
|
||||
.DOA(DO_A), \
|
||||
.DIA(DI_A), \
|
||||
.CLKB(PORT_B_CLK), \
|
||||
.ENB(PORT_B_CLK_EN), \
|
||||
.WEB(PORT_B_WR_EN), \
|
||||
.SSRB(PORT_B_RD_SRST), \
|
||||
.ADDRB(PORT_B_ADDR addr_slice_b), \
|
||||
.DOB(DO_B), \
|
||||
.DIB(DI_B),
|
||||
|
||||
`define PORTS_DP_SWAP(addr_slice_a, addr_slice_b) \
|
||||
.CLKB(PORT_A_CLK), \
|
||||
.ENB(PORT_A_CLK_EN), \
|
||||
.WEB(PORT_A_WR_EN), \
|
||||
.SSRB(PORT_A_RD_SRST), \
|
||||
.ADDRB(PORT_A_ADDR addr_slice_a), \
|
||||
.DOB(DO_A), \
|
||||
.DIB(DI_A), \
|
||||
.CLKA(PORT_B_CLK), \
|
||||
.ENA(PORT_B_CLK_EN), \
|
||||
.WEA(PORT_B_WR_EN), \
|
||||
.SSRA(PORT_B_RD_SRST), \
|
||||
.ADDRA(PORT_B_ADDR addr_slice_b), \
|
||||
.DOA(DO_B), \
|
||||
.DIA(DI_B),
|
||||
|
||||
`define PORTS_SP(addr_slice) \
|
||||
.CLK(PORT_A_CLK), \
|
||||
.EN(PORT_A_CLK_EN), \
|
||||
.WE(PORT_A_WR_EN), \
|
||||
.SSR(PORT_A_RD_SRST), \
|
||||
.ADDR(PORT_A_ADDR addr_slice), \
|
||||
.DO(DO_A), \
|
||||
.DI(DI_A),
|
||||
|
||||
localparam [PORT_A_WIDTH-1:0] SRVAL_A = ival(PORT_A_WIDTH, PORT_A_RD_SRST_VALUE);
|
||||
localparam [PORT_B_WIDTH-1:0] SRVAL_B = ival(PORT_B_WIDTH, PORT_B_RD_SRST_VALUE);
|
||||
localparam [PORT_A_WIDTH-1:0] INIT_A = ival(PORT_A_WIDTH, PORT_A_RD_INIT_VALUE);
|
||||
localparam [PORT_B_WIDTH-1:0] INIT_B = ival(PORT_B_WIDTH, PORT_B_RD_INIT_VALUE);
|
||||
|
||||
`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
|
||||
`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
|
||||
`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
|
||||
`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_USE_BE) begin
|
||||
if (!PORT_B_USED) begin
|
||||
case (PORT_A_WIDTH)
|
||||
9: RAMB16_S9 #(
|
||||
`PARAMS_SP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:3])
|
||||
.DIP(DIP_A),
|
||||
.DOP(DOP_A),
|
||||
);
|
||||
18: RAMB16BWE_S18 #(
|
||||
`PARAMS_SP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:4])
|
||||
.DIP(DIP_A),
|
||||
.DOP(DOP_A),
|
||||
);
|
||||
36: RAMB16BWE_S36 #(
|
||||
`PARAMS_SP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:5])
|
||||
.DIP(DIP_A),
|
||||
.DOP(DOP_A),
|
||||
);
|
||||
endcase
|
||||
end else begin
|
||||
case (PORT_A_WIDTH)
|
||||
9: case(PORT_B_WIDTH)
|
||||
9: RAMB16_S9_S9 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:3], [13:3])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
18: RAMB16BWE_S9_S18 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:3], [13:4])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
36: RAMB16BWE_S9_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:3], [13:5])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
18: case(PORT_B_WIDTH)
|
||||
9: RAMB16BWE_S9_S18 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:4], [13:3])
|
||||
.DIPA(DIP_B), .DOPA(DOP_B),
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
18: RAMB16BWE_S18_S18 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:4], [13:4])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
36: RAMB16BWE_S18_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:4], [13:5])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
36: case(PORT_B_WIDTH)
|
||||
9: RAMB16BWE_S9_S36 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:5], [13:3])
|
||||
.DIPA(DIP_B), .DOPA(DOP_B),
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
18: RAMB16BWE_S18_S36 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:5], [13:4])
|
||||
.DIPA(DIP_B), .DOPA(DOP_B),
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
36: RAMB16BWE_S36_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:5], [13:5])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
end else begin
|
||||
if (!PORT_B_USED) begin
|
||||
case (PORT_A_WIDTH)
|
||||
1: RAMB16_S1 #(
|
||||
`PARAMS_SP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:0])
|
||||
);
|
||||
2: RAMB16_S2 #(
|
||||
`PARAMS_SP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:1])
|
||||
);
|
||||
4: RAMB16_S4 #(
|
||||
`PARAMS_SP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:2])
|
||||
);
|
||||
9: RAMB16_S9 #(
|
||||
`PARAMS_SP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:3])
|
||||
.DIP(DIP_A),
|
||||
.DOP(DOP_A),
|
||||
);
|
||||
18: RAMB16_S18 #(
|
||||
`PARAMS_SP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:4])
|
||||
.DIP(DIP_A),
|
||||
.DOP(DOP_A),
|
||||
);
|
||||
36: RAMB16_S36 #(
|
||||
`PARAMS_SP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([13:5])
|
||||
.DIP(DIP_A),
|
||||
.DOP(DOP_A),
|
||||
);
|
||||
endcase
|
||||
end else begin
|
||||
case (PORT_A_WIDTH)
|
||||
1: case(PORT_B_WIDTH)
|
||||
1: RAMB16_S1_S1 #(
|
||||
`PARAMS_DP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:0], [13:0])
|
||||
);
|
||||
2: RAMB16_S1_S2 #(
|
||||
`PARAMS_DP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:0], [13:1])
|
||||
);
|
||||
4: RAMB16_S1_S4 #(
|
||||
`PARAMS_DP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:0], [13:2])
|
||||
);
|
||||
9: RAMB16_S1_S9 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:0], [13:3])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
18: RAMB16_S1_S18 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:0], [13:4])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
36: RAMB16_S1_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:0], [13:5])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
2: case(PORT_B_WIDTH)
|
||||
1: RAMB16_S1_S2 #(
|
||||
`PARAMS_DP_SWAP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:1], [13:0])
|
||||
);
|
||||
2: RAMB16_S2_S2 #(
|
||||
`PARAMS_DP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:1], [13:1])
|
||||
);
|
||||
4: RAMB16_S2_S4 #(
|
||||
`PARAMS_DP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:1], [13:2])
|
||||
);
|
||||
9: RAMB16_S2_S9 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:1], [13:3])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
18: RAMB16_S2_S18 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:1], [13:4])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
36: RAMB16_S2_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:1], [13:5])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
4: case(PORT_B_WIDTH)
|
||||
1: RAMB16_S1_S4 #(
|
||||
`PARAMS_DP_SWAP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:2], [13:0])
|
||||
);
|
||||
2: RAMB16_S2_S4 #(
|
||||
`PARAMS_DP_SWAP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:2], [13:1])
|
||||
);
|
||||
4: RAMB16_S4_S4 #(
|
||||
`PARAMS_DP
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:2], [13:2])
|
||||
);
|
||||
9: RAMB16_S4_S9 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:2], [13:3])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
18: RAMB16_S4_S18 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:2], [13:4])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
36: RAMB16_S4_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:2], [13:5])
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
9: case(PORT_B_WIDTH)
|
||||
1: RAMB16_S1_S9 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:3], [13:0])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
2: RAMB16_S2_S9 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:3], [13:1])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
4: RAMB16_S4_S9 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:3], [13:2])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
9: RAMB16_S9_S9 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:3], [13:3])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
18: RAMB16_S9_S18 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:3], [13:4])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
36: RAMB16_S9_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:3], [13:5])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
18: case(PORT_B_WIDTH)
|
||||
1: RAMB16_S1_S18 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:4], [13:0])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
2: RAMB16_S2_S18 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:4], [13:1])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
4: RAMB16_S4_S18 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:4], [13:2])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
9: RAMB16_S9_S18 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:4], [13:3])
|
||||
.DIPA(DIP_B), .DOPA(DOP_B),
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
18: RAMB16_S18_S18 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:4], [13:4])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
36: RAMB16_S18_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:4], [13:5])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
36: case(PORT_B_WIDTH)
|
||||
1: RAMB16_S1_S36 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:5], [13:0])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
2: RAMB16_S2_S36 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:5], [13:1])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
4: RAMB16_S4_S36 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:5], [13:2])
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
9: RAMB16_S9_S36 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:5], [13:3])
|
||||
.DIPA(DIP_B), .DOPA(DOP_B),
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
18: RAMB16_S18_S36 #(
|
||||
`PARAMS_DP_SWAP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([13:5], [13:4])
|
||||
.DIPA(DIP_B), .DOPA(DOP_B),
|
||||
.DIPB(DIP_A), .DOPB(DOP_A),
|
||||
);
|
||||
36: RAMB16_S36_S36 #(
|
||||
`PARAMS_DP
|
||||
`PARAMS_INITP_18
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([13:5], [13:5])
|
||||
.DIPA(DIP_A), .DOPA(DOP_A),
|
||||
.DIPB(DIP_B), .DOPB(DOP_B),
|
||||
);
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
# Block RAMs for Spartan 3A DSP and Spartan 6.
|
||||
# The corresponding mapping file is brams_xc3sda_map.v
|
||||
|
||||
ram block $__XILINX_BLOCKRAM_TDP_ {
|
||||
byte 9;
|
||||
ifdef IS_SPARTAN6 {
|
||||
option "MODE" "HALF" {
|
||||
abits 13;
|
||||
widths 1 2 4 9 18 per_port;
|
||||
cost 65;
|
||||
}
|
||||
}
|
||||
option "MODE" "FULL" {
|
||||
abits 14;
|
||||
widths 1 2 4 9 18 36 per_port;
|
||||
cost 129;
|
||||
}
|
||||
init any;
|
||||
port srsw "A" "B" {
|
||||
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
|
||||
ifdef IS_SPARTAN6 {
|
||||
option "HAS_RDFIRST" 1 {
|
||||
clock posedge "C";
|
||||
}
|
||||
option "HAS_RDFIRST" 0 {
|
||||
clock posedge;
|
||||
}
|
||||
} else {
|
||||
clock posedge;
|
||||
}
|
||||
clken;
|
||||
option "RSTTYPE" "SYNC" {
|
||||
portoption "RST_PRIORITY" "CE" {
|
||||
rdsrst any gated_clken;
|
||||
}
|
||||
ifdef IS_SPARTAN6 {
|
||||
portoption "RST_PRIORITY" "SR" {
|
||||
rdsrst any ungated;
|
||||
}
|
||||
}
|
||||
}
|
||||
ifdef IS_SPARTAN6 {
|
||||
option "RSTTYPE" "ASYNC" {
|
||||
portoption "RST_PRIORITY" "SR" {
|
||||
rdarst any;
|
||||
}
|
||||
}
|
||||
}
|
||||
rdinit any;
|
||||
portoption "WRITE_MODE" "NO_CHANGE" {
|
||||
rdwr no_change;
|
||||
}
|
||||
portoption "WRITE_MODE" "WRITE_FIRST" {
|
||||
rdwr new;
|
||||
}
|
||||
ifdef IS_SPARTAN6 {
|
||||
option "HAS_RDFIRST" 1 {
|
||||
portoption "WRITE_MODE" "READ_FIRST" {
|
||||
rdwr old;
|
||||
wrtrans all old;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
portoption "WRITE_MODE" "READ_FIRST" {
|
||||
rdwr old;
|
||||
wrtrans all old;
|
||||
}
|
||||
}
|
||||
optional;
|
||||
}
|
||||
}
|
||||
|
||||
ifdef IS_SPARTAN6 {
|
||||
ram block $__XILINX_BLOCKRAM_SDP_ {
|
||||
byte 9;
|
||||
abits 13;
|
||||
widths 1 2 4 9 18 36 per_port;
|
||||
cost 65;
|
||||
init any;
|
||||
port sw "W" {
|
||||
width 36;
|
||||
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
|
||||
option "WRITE_MODE" "READ_FIRST" {
|
||||
clock posedge "C";
|
||||
wrtrans all old;
|
||||
}
|
||||
option "WRITE_MODE" "WRITE_FIRST" {
|
||||
clock posedge;
|
||||
}
|
||||
clken;
|
||||
optional;
|
||||
}
|
||||
port sr "R" {
|
||||
width 36;
|
||||
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
|
||||
option "WRITE_MODE" "READ_FIRST" {
|
||||
clock posedge "C";
|
||||
}
|
||||
option "WRITE_MODE" "WRITE_FIRST" {
|
||||
clock posedge;
|
||||
}
|
||||
clken;
|
||||
option "RSTTYPE" "SYNC" {
|
||||
portoption "RST_PRIORITY" "CE" {
|
||||
rdsrst any gated_clken;
|
||||
}
|
||||
portoption "RST_PRIORITY" "SR" {
|
||||
rdsrst any ungated;
|
||||
}
|
||||
}
|
||||
option "RSTTYPE" "ASYNC" {
|
||||
portoption "RST_PRIORITY" "SR" {
|
||||
rdarst any;
|
||||
}
|
||||
}
|
||||
rdinit any;
|
||||
optional;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
module $__XILINX_BLOCKRAM_TDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_MODE = "FULL";
|
||||
parameter OPTION_RSTTYPE = "SYNC";
|
||||
parameter OPTION_HAS_RDFIRST = 0;
|
||||
|
||||
parameter PORT_A_WIDTH = 1;
|
||||
parameter PORT_A_WR_EN_WIDTH = 1;
|
||||
parameter PORT_A_USED = 1;
|
||||
parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_A_RD_INIT_VALUE = 0;
|
||||
parameter PORT_A_RD_SRST_VALUE = 0;
|
||||
parameter PORT_A_RD_ARST_VALUE = 0;
|
||||
parameter PORT_A_OPTION_RST_PRIORITY = "CE";
|
||||
|
||||
parameter PORT_B_WIDTH = 1;
|
||||
parameter PORT_B_WR_EN_WIDTH = 1;
|
||||
parameter PORT_B_USED = 0;
|
||||
parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_B_RD_INIT_VALUE = 0;
|
||||
parameter PORT_B_RD_SRST_VALUE = 0;
|
||||
parameter PORT_B_RD_ARST_VALUE = 0;
|
||||
parameter PORT_B_OPTION_RST_PRIORITY = "CE";
|
||||
|
||||
input CLK_C;
|
||||
|
||||
input PORT_A_CLK;
|
||||
input PORT_A_CLK_EN;
|
||||
input [13:0] PORT_A_ADDR;
|
||||
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
|
||||
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
|
||||
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
|
||||
input PORT_A_RD_SRST;
|
||||
input PORT_A_RD_ARST;
|
||||
|
||||
input PORT_B_CLK;
|
||||
input PORT_B_CLK_EN;
|
||||
input [13:0] PORT_B_ADDR;
|
||||
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
|
||||
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
|
||||
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
|
||||
input PORT_B_RD_SRST;
|
||||
input PORT_B_RD_ARST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_COMMON \
|
||||
.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
|
||||
.DATA_WIDTH_A(PORT_A_USED ? PORT_A_WIDTH : 0), \
|
||||
.DATA_WIDTH_B(PORT_B_USED ? PORT_B_WIDTH : 0), \
|
||||
.EN_RSTRAM_A("TRUE"), \
|
||||
.EN_RSTRAM_B("TRUE"), \
|
||||
.DOA_REG(0), \
|
||||
.DOB_REG(0), \
|
||||
.RST_PRIORITY_A(PORT_A_OPTION_RST_PRIORITY), \
|
||||
.RST_PRIORITY_B(PORT_B_OPTION_RST_PRIORITY), \
|
||||
.RSTTYPE(OPTION_RSTTYPE), \
|
||||
.INIT_A(ival(PORT_A_WIDTH, PORT_A_RD_INIT_VALUE)), \
|
||||
.INIT_B(ival(PORT_B_WIDTH, PORT_B_RD_INIT_VALUE)), \
|
||||
.SRVAL_A(ival(PORT_A_WIDTH, OPTION_RSTTYPE == "SYNC" ? PORT_A_RD_SRST_VALUE : PORT_A_RD_ARST_VALUE)), \
|
||||
.SRVAL_B(ival(PORT_B_WIDTH, OPTION_RSTTYPE == "SYNC" ? PORT_B_RD_SRST_VALUE : PORT_B_RD_ARST_VALUE)),
|
||||
|
||||
wire RST_A = OPTION_RSTTYPE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
|
||||
wire RST_B = OPTION_RSTTYPE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
|
||||
|
||||
`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
|
||||
`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
|
||||
`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
|
||||
`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_MODE == "FULL") begin
|
||||
wire [3:0] WE_A = {4{PORT_A_WR_EN}};
|
||||
wire [3:0] WE_B = {4{PORT_B_WR_EN}};
|
||||
RAMB16BWER #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_INITP_18
|
||||
`PARAMS_COMMON
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOA(DO_A),
|
||||
.DOPA(DOP_A),
|
||||
.DIA(DI_A),
|
||||
.DIPA(DIP_A),
|
||||
.DOB(DO_B),
|
||||
.DOPB(DOP_B),
|
||||
.DIB(DI_B),
|
||||
.DIPB(DIP_B),
|
||||
.ADDRA(PORT_A_ADDR),
|
||||
.ADDRB(PORT_B_ADDR),
|
||||
.CLKA(PORT_A_CLK),
|
||||
.CLKB(PORT_B_CLK),
|
||||
.ENA(PORT_A_CLK_EN),
|
||||
.ENB(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.RSTA(RST_A),
|
||||
.RSTB(RST_B),
|
||||
.WEA(WE_A),
|
||||
.WEB(WE_B),
|
||||
);
|
||||
end else begin
|
||||
wire [1:0] WE_A = {2{PORT_A_WR_EN}};
|
||||
wire [1:0] WE_B = {2{PORT_B_WR_EN}};
|
||||
RAMB8BWER #(
|
||||
`PARAMS_INIT_9
|
||||
`PARAMS_INITP_9
|
||||
`PARAMS_COMMON
|
||||
.RAM_MODE("TDP"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOADO(DO_A),
|
||||
.DOPADOP(DOP_A),
|
||||
.DIADI(DI_A),
|
||||
.DIPADIP(DIP_A),
|
||||
.DOBDO(DO_B),
|
||||
.DOPBDOP(DOP_B),
|
||||
.DIBDI(DI_B),
|
||||
.DIPBDIP(DIP_B),
|
||||
.ADDRAWRADDR(PORT_A_ADDR),
|
||||
.ADDRBRDADDR(PORT_B_ADDR),
|
||||
.CLKAWRCLK(PORT_A_CLK),
|
||||
.CLKBRDCLK(PORT_B_CLK),
|
||||
.ENAWREN(PORT_A_CLK_EN),
|
||||
.ENBRDEN(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEBREGCE(1'b0),
|
||||
.RSTA(RST_A),
|
||||
.RSTBRST(RST_B),
|
||||
.WEAWEL(WE_A),
|
||||
.WEBWEU(WE_B),
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_BLOCKRAM_SDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_RSTTYPE = "SYNC";
|
||||
parameter OPTION_WRITE_MODE = "READ_FIRST";
|
||||
|
||||
parameter PORT_W_WIDTH = 1;
|
||||
parameter PORT_W_WR_EN_WIDTH = 1;
|
||||
parameter PORT_W_USED = 1;
|
||||
|
||||
parameter PORT_R_WIDTH = 1;
|
||||
parameter PORT_R_USED = 0;
|
||||
parameter PORT_R_RD_INIT_VALUE = 0;
|
||||
parameter PORT_R_RD_SRST_VALUE = 0;
|
||||
parameter PORT_R_RD_ARST_VALUE = 0;
|
||||
parameter PORT_R_OPTION_RST_PRIORITY = "CE";
|
||||
|
||||
input CLK_C;
|
||||
|
||||
input PORT_W_CLK;
|
||||
input PORT_W_CLK_EN;
|
||||
input [13:0] PORT_W_ADDR;
|
||||
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
|
||||
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
|
||||
|
||||
input PORT_R_CLK;
|
||||
input PORT_R_CLK_EN;
|
||||
input [13:0] PORT_R_ADDR;
|
||||
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
|
||||
input PORT_R_RD_SRST;
|
||||
input PORT_R_RD_ARST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
wire RST = OPTION_RSTTYPE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
|
||||
|
||||
`MAKE_DI(DI, DIP, PORT_W_WR_DATA)
|
||||
`MAKE_DO(DO, DOP, PORT_R_RD_DATA)
|
||||
|
||||
localparam [35:0] RST_VALUE = OPTION_RSTTYPE == "SYNC" ? PORT_R_RD_SRST_VALUE : PORT_R_RD_ARST_VALUE;
|
||||
|
||||
RAMB8BWER #(
|
||||
`PARAMS_INIT_9
|
||||
`PARAMS_INITP_9
|
||||
.WRITE_MODE_A(OPTION_WRITE_MODE),
|
||||
.WRITE_MODE_B(OPTION_WRITE_MODE),
|
||||
.DATA_WIDTH_A(PORT_W_USED ? PORT_W_WIDTH : 0),
|
||||
.DATA_WIDTH_B(PORT_R_USED ? PORT_R_WIDTH : 0),
|
||||
.EN_RSTRAM_A("TRUE"),
|
||||
.EN_RSTRAM_B("TRUE"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.RST_PRIORITY_A("CE"),
|
||||
.RST_PRIORITY_B(PORT_R_OPTION_RST_PRIORITY),
|
||||
.RSTTYPE(OPTION_RSTTYPE),
|
||||
.INIT_A(ival(18, PORT_R_RD_INIT_VALUE[17:0])),
|
||||
.INIT_B(ival(18, PORT_R_RD_INIT_VALUE[35:18])),
|
||||
.SRVAL_A(ival(18, RST_VALUE[17:0])),
|
||||
.SRVAL_B(ival(18, RST_VALUE[35:18])),
|
||||
.RAM_MODE("SDP"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOADO(DO[15:0]),
|
||||
.DOPADOP(DOP[1:0]),
|
||||
.DIADI(DI[15:0]),
|
||||
.DIPADIP(DIP[1:0]),
|
||||
.DOBDO(DO[31:16]),
|
||||
.DOPBDOP(DOP[3:2]),
|
||||
.DIBDI(DI[31:16]),
|
||||
.DIPBDIP(DIP[3:2]),
|
||||
.ADDRAWRADDR(PORT_W_ADDR),
|
||||
.ADDRBRDADDR(PORT_R_ADDR),
|
||||
.CLKAWRCLK(PORT_W_CLK),
|
||||
.CLKBRDCLK(PORT_R_CLK),
|
||||
.ENAWREN(PORT_W_CLK_EN),
|
||||
.ENBRDEN(PORT_R_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEBREGCE(1'b0),
|
||||
.RSTA(1'b0),
|
||||
.RSTBRST(RST),
|
||||
.WEAWEL(PORT_W_WR_EN[1:0]),
|
||||
.WEBWEU(PORT_W_WR_EN[3:2]),
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
# Block RAMs for Virtex 4+.
|
||||
# The corresponding mapping files are:
|
||||
# - brams_xc3sda_map.v: Spartan 3A DSP, Spartan 6
|
||||
# - brams_xc4v_map.v: Virtex 4
|
||||
# - brams_xc5v_map.v: Virtex 5
|
||||
# - brams_xc6v_map.v: Virtex 6, Series 7
|
||||
# - brams_xcu_map.v: Ultrascale
|
||||
|
||||
ram block $__XILINX_BLOCKRAM_TDP_ {
|
||||
byte 9;
|
||||
ifdef HAS_SIZE_36 {
|
||||
option "MODE" "HALF" {
|
||||
abits 14;
|
||||
widths 1 2 4 9 18 per_port;
|
||||
cost 129;
|
||||
}
|
||||
option "MODE" "FULL" {
|
||||
abits 15;
|
||||
widths 1 2 4 9 18 36 per_port;
|
||||
cost 257;
|
||||
}
|
||||
ifdef HAS_CASCADE {
|
||||
option "MODE" "CASCADE" {
|
||||
abits 16;
|
||||
# hack to enforce same INIT layout as in the other modes
|
||||
widths 1 2 4 9 per_port;
|
||||
cost 513;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
option "MODE" "FULL" {
|
||||
abits 14;
|
||||
widths 1 2 4 9 18 36 per_port;
|
||||
cost 129;
|
||||
}
|
||||
ifdef HAS_CASCADE {
|
||||
option "MODE" "CASCADE" {
|
||||
abits 15;
|
||||
widths 1 2 4 9 per_port;
|
||||
cost 257;
|
||||
}
|
||||
}
|
||||
}
|
||||
init any;
|
||||
port srsw "A" "B" {
|
||||
option "MODE" "HALF" {
|
||||
width mix;
|
||||
}
|
||||
option "MODE" "FULL" {
|
||||
width mix;
|
||||
}
|
||||
option "MODE" "CASCADE" {
|
||||
width mix 1;
|
||||
}
|
||||
ifdef HAS_ADDRCE {
|
||||
# TODO
|
||||
# addrce;
|
||||
}
|
||||
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
|
||||
ifdef HAS_CONFLICT_BUG {
|
||||
option "HAS_RDFIRST" 1 {
|
||||
clock posedge "C";
|
||||
}
|
||||
option "HAS_RDFIRST" 0 {
|
||||
clock posedge;
|
||||
}
|
||||
} else {
|
||||
clock posedge;
|
||||
}
|
||||
clken;
|
||||
rdsrst any gated_clken;
|
||||
rdinit any;
|
||||
portoption "WRITE_MODE" "NO_CHANGE" {
|
||||
rdwr no_change;
|
||||
option "MODE" "CASCADE" {
|
||||
forbid;
|
||||
}
|
||||
}
|
||||
portoption "WRITE_MODE" "WRITE_FIRST" {
|
||||
ifdef HAS_SIZE_36 {
|
||||
rdwr new;
|
||||
} else {
|
||||
rdwr new_only;
|
||||
}
|
||||
}
|
||||
ifdef HAS_CONFLICT_BUG {
|
||||
option "HAS_RDFIRST" 1 {
|
||||
portoption "WRITE_MODE" "READ_FIRST" {
|
||||
rdwr old;
|
||||
wrtrans all old;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
portoption "WRITE_MODE" "READ_FIRST" {
|
||||
rdwr old;
|
||||
wrtrans all old;
|
||||
}
|
||||
}
|
||||
optional_rw;
|
||||
}
|
||||
}
|
||||
|
||||
ifdef HAS_SIZE_36 {
|
||||
ram block $__XILINX_BLOCKRAM_SDP_ {
|
||||
byte 9;
|
||||
option "MODE" "HALF" {
|
||||
abits 14;
|
||||
widths 1 2 4 9 18 36 per_port;
|
||||
cost 129;
|
||||
}
|
||||
option "MODE" "FULL" {
|
||||
abits 15;
|
||||
widths 1 2 4 9 18 36 72 per_port;
|
||||
cost 257;
|
||||
}
|
||||
init any;
|
||||
port sw "W" {
|
||||
ifndef HAS_MIXWIDTH_SDP {
|
||||
option "MODE" "HALF" width 36;
|
||||
option "MODE" "FULL" width 72;
|
||||
}
|
||||
ifdef HAS_ADDRCE {
|
||||
# TODO
|
||||
# addrce;
|
||||
}
|
||||
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
|
||||
ifdef HAS_CONFLICT_BUG {
|
||||
option "WRITE_MODE" "READ_FIRST" {
|
||||
clock posedge "C";
|
||||
}
|
||||
option "WRITE_MODE" "WRITE_FIRST" {
|
||||
clock posedge;
|
||||
}
|
||||
} else {
|
||||
clock posedge;
|
||||
}
|
||||
clken;
|
||||
option "WRITE_MODE" "READ_FIRST" {
|
||||
wrtrans all old;
|
||||
}
|
||||
optional;
|
||||
}
|
||||
port sr "R" {
|
||||
ifndef HAS_MIXWIDTH_SDP {
|
||||
option "MODE" "HALF" width 36;
|
||||
option "MODE" "FULL" width 72;
|
||||
}
|
||||
ifdef HAS_ADDRCE {
|
||||
# TODO
|
||||
# addrce;
|
||||
}
|
||||
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
|
||||
ifdef HAS_CONFLICT_BUG {
|
||||
option "WRITE_MODE" "READ_FIRST" {
|
||||
clock posedge "C";
|
||||
}
|
||||
option "WRITE_MODE" "WRITE_FIRST" {
|
||||
clock posedge;
|
||||
}
|
||||
} else {
|
||||
clock posedge;
|
||||
}
|
||||
clken;
|
||||
rdsrst any gated_clken;
|
||||
rdinit any;
|
||||
optional;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
module $__XILINX_BLOCKRAM_TDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_MODE = "FULL";
|
||||
|
||||
parameter PORT_A_RD_WIDTH = 1;
|
||||
parameter PORT_A_WR_WIDTH = 1;
|
||||
parameter PORT_A_WR_EN_WIDTH = 1;
|
||||
parameter PORT_A_RD_USED = 1;
|
||||
parameter PORT_A_WR_USED = 1;
|
||||
parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_A_RD_INIT_VALUE = 0;
|
||||
parameter PORT_A_RD_SRST_VALUE = 0;
|
||||
|
||||
parameter PORT_B_RD_WIDTH = 1;
|
||||
parameter PORT_B_WR_WIDTH = 1;
|
||||
parameter PORT_B_WR_EN_WIDTH = 1;
|
||||
parameter PORT_B_RD_USED = 0;
|
||||
parameter PORT_B_WR_USED = 0;
|
||||
parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_B_RD_INIT_VALUE = 0;
|
||||
parameter PORT_B_RD_SRST_VALUE = 0;
|
||||
|
||||
input PORT_A_CLK;
|
||||
input PORT_A_CLK_EN;
|
||||
input [14:0] PORT_A_ADDR;
|
||||
input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;
|
||||
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
|
||||
output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;
|
||||
input PORT_A_RD_SRST;
|
||||
|
||||
input PORT_B_CLK;
|
||||
input PORT_B_CLK_EN;
|
||||
input [14:0] PORT_B_ADDR;
|
||||
input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;
|
||||
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
|
||||
output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;
|
||||
input PORT_B_RD_SRST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_COMMON \
|
||||
.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
|
||||
.READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \
|
||||
.READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \
|
||||
.WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \
|
||||
.WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \
|
||||
.DOA_REG(0), \
|
||||
.DOB_REG(0), \
|
||||
.INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \
|
||||
.INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \
|
||||
.SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \
|
||||
.SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)),
|
||||
|
||||
`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
|
||||
`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
|
||||
`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
|
||||
`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
|
||||
|
||||
wire [3:0] WE_A = {4{PORT_A_WR_EN}};
|
||||
wire [3:0] WE_B = {4{PORT_B_WR_EN}};
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_MODE == "FULL") begin
|
||||
RAMB16 #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_INITP_18
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("NONE"),
|
||||
.RAM_EXTENSION_B("NONE"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOA(DO_A),
|
||||
.DOPA(DOP_A),
|
||||
.DIA(DI_A),
|
||||
.DIPA(DIP_A),
|
||||
.DOB(DO_B),
|
||||
.DOPB(DOP_B),
|
||||
.DIB(DI_B),
|
||||
.DIPB(DIP_B),
|
||||
.ADDRA({1'b1, PORT_A_ADDR[13:0]}),
|
||||
.ADDRB({1'b1, PORT_B_ADDR[13:0]}),
|
||||
.CLKA(PORT_A_CLK),
|
||||
.CLKB(PORT_B_CLK),
|
||||
.ENA(PORT_A_CLK_EN),
|
||||
.ENB(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.SSRA(PORT_A_RD_SRST),
|
||||
.SSRB(PORT_B_RD_SRST),
|
||||
.WEA(WE_A),
|
||||
.WEB(WE_B),
|
||||
);
|
||||
end else begin
|
||||
wire CAS_A, CAS_B;
|
||||
RAMB16 #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("LOWER"),
|
||||
.RAM_EXTENSION_B("LOWER"),
|
||||
) lower (
|
||||
.DIA(DI_A),
|
||||
.DIB(DI_B),
|
||||
.ADDRA(PORT_A_ADDR),
|
||||
.ADDRB(PORT_B_ADDR),
|
||||
.CLKA(PORT_A_CLK),
|
||||
.CLKB(PORT_B_CLK),
|
||||
.ENA(PORT_A_CLK_EN),
|
||||
.ENB(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.SSRA(PORT_A_RD_SRST),
|
||||
.SSRB(PORT_B_RD_SRST),
|
||||
.WEA(WE_A),
|
||||
.WEB(WE_B),
|
||||
.CASCADEOUTA(CAS_A),
|
||||
.CASCADEOUTB(CAS_B),
|
||||
);
|
||||
RAMB16 #(
|
||||
`PARAMS_INIT_18_U
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("UPPER"),
|
||||
.RAM_EXTENSION_B("UPPER"),
|
||||
) upper (
|
||||
.DOA(DO_A),
|
||||
.DIA(DI_A),
|
||||
.DOB(DO_B),
|
||||
.DIB(DI_B),
|
||||
.ADDRA(PORT_A_ADDR),
|
||||
.ADDRB(PORT_B_ADDR),
|
||||
.CLKA(PORT_A_CLK),
|
||||
.CLKB(PORT_B_CLK),
|
||||
.ENA(PORT_A_CLK_EN),
|
||||
.ENB(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.SSRA(PORT_A_RD_SRST),
|
||||
.SSRB(PORT_B_RD_SRST),
|
||||
.WEA(WE_A),
|
||||
.WEB(WE_B),
|
||||
.CASCADEINA(CAS_A),
|
||||
.CASCADEINB(CAS_B),
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
module $__XILINX_BLOCKRAM_TDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_MODE = "FULL";
|
||||
|
||||
parameter PORT_A_RD_WIDTH = 1;
|
||||
parameter PORT_A_WR_WIDTH = 1;
|
||||
parameter PORT_A_WR_EN_WIDTH = 1;
|
||||
parameter PORT_A_RD_USED = 1;
|
||||
parameter PORT_A_WR_USED = 1;
|
||||
parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_A_RD_INIT_VALUE = 0;
|
||||
parameter PORT_A_RD_SRST_VALUE = 0;
|
||||
|
||||
parameter PORT_B_RD_WIDTH = 1;
|
||||
parameter PORT_B_WR_WIDTH = 1;
|
||||
parameter PORT_B_WR_EN_WIDTH = 1;
|
||||
parameter PORT_B_RD_USED = 0;
|
||||
parameter PORT_B_WR_USED = 0;
|
||||
parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_B_RD_INIT_VALUE = 0;
|
||||
parameter PORT_B_RD_SRST_VALUE = 0;
|
||||
|
||||
input PORT_A_CLK;
|
||||
input PORT_A_CLK_EN;
|
||||
input [15:0] PORT_A_ADDR;
|
||||
input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;
|
||||
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
|
||||
output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;
|
||||
input PORT_A_RD_SRST;
|
||||
|
||||
input PORT_B_CLK;
|
||||
input PORT_B_CLK_EN;
|
||||
input [15:0] PORT_B_ADDR;
|
||||
input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;
|
||||
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
|
||||
output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;
|
||||
input PORT_B_RD_SRST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_COMMON \
|
||||
.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
|
||||
.READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \
|
||||
.READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \
|
||||
.WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \
|
||||
.WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \
|
||||
.DOA_REG(0), \
|
||||
.DOB_REG(0), \
|
||||
.INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \
|
||||
.INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \
|
||||
.SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \
|
||||
.SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)),
|
||||
|
||||
`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
|
||||
`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
|
||||
`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
|
||||
`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
|
||||
|
||||
wire [3:0] WE_A = {4{PORT_A_WR_EN}};
|
||||
wire [3:0] WE_B = {4{PORT_B_WR_EN}};
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_MODE == "HALF") begin
|
||||
RAMB18 #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_INITP_18
|
||||
`PARAMS_COMMON
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOA(DO_A),
|
||||
.DOPA(DOP_A),
|
||||
.DIA(DI_A),
|
||||
.DIPA(DIP_A),
|
||||
.DOB(DO_B),
|
||||
.DOPB(DOP_B),
|
||||
.DIB(DI_B),
|
||||
.DIPB(DIP_B),
|
||||
.ADDRA(PORT_A_ADDR[13:0]),
|
||||
.ADDRB(PORT_B_ADDR[13:0]),
|
||||
.CLKA(PORT_A_CLK),
|
||||
.CLKB(PORT_B_CLK),
|
||||
.ENA(PORT_A_CLK_EN),
|
||||
.ENB(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.SSRA(PORT_A_RD_SRST),
|
||||
.SSRB(PORT_B_RD_SRST),
|
||||
.WEA(WE_A),
|
||||
.WEB(WE_B),
|
||||
);
|
||||
end else if (OPTION_MODE == "FULL") begin
|
||||
RAMB36 #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_INITP_36
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("NONE"),
|
||||
.RAM_EXTENSION_B("NONE"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOA(DO_A),
|
||||
.DOPA(DOP_A),
|
||||
.DIA(DI_A),
|
||||
.DIPA(DIP_A),
|
||||
.DOB(DO_B),
|
||||
.DOPB(DOP_B),
|
||||
.DIB(DI_B),
|
||||
.DIPB(DIP_B),
|
||||
.ADDRA({1'b1, PORT_A_ADDR[14:0]}),
|
||||
.ADDRB({1'b1, PORT_B_ADDR[14:0]}),
|
||||
.CLKA(PORT_A_CLK),
|
||||
.CLKB(PORT_B_CLK),
|
||||
.ENA(PORT_A_CLK_EN),
|
||||
.ENB(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.SSRA(PORT_A_RD_SRST),
|
||||
.SSRB(PORT_B_RD_SRST),
|
||||
.WEA(WE_A),
|
||||
.WEB(WE_B),
|
||||
);
|
||||
end else begin
|
||||
wire CAS_A, CAS_B;
|
||||
RAMB36 #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("LOWER"),
|
||||
.RAM_EXTENSION_B("LOWER"),
|
||||
) lower (
|
||||
.DIA(DI_A),
|
||||
.DIB(DI_B),
|
||||
.ADDRA(PORT_A_ADDR),
|
||||
.ADDRB(PORT_B_ADDR),
|
||||
.CLKA(PORT_A_CLK),
|
||||
.CLKB(PORT_B_CLK),
|
||||
.ENA(PORT_A_CLK_EN),
|
||||
.ENB(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.SSRA(PORT_A_RD_SRST),
|
||||
.SSRB(PORT_B_RD_SRST),
|
||||
.WEA(WE_A),
|
||||
.WEB(WE_B),
|
||||
.CASCADEOUTLATA(CAS_A),
|
||||
.CASCADEOUTLATB(CAS_B),
|
||||
);
|
||||
RAMB36 #(
|
||||
`PARAMS_INIT_36_U
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("UPPER"),
|
||||
.RAM_EXTENSION_B("UPPER"),
|
||||
) upper (
|
||||
.DOA(DO_A),
|
||||
.DIA(DI_A),
|
||||
.DOB(DO_B),
|
||||
.DIB(DI_B),
|
||||
.ADDRA(PORT_A_ADDR),
|
||||
.ADDRB(PORT_B_ADDR),
|
||||
.CLKA(PORT_A_CLK),
|
||||
.CLKB(PORT_B_CLK),
|
||||
.ENA(PORT_A_CLK_EN),
|
||||
.ENB(PORT_B_CLK_EN),
|
||||
.REGCEA(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.SSRA(PORT_A_RD_SRST),
|
||||
.SSRB(PORT_B_RD_SRST),
|
||||
.WEA(WE_A),
|
||||
.WEB(WE_B),
|
||||
.CASCADEINLATA(CAS_A),
|
||||
.CASCADEINLATB(CAS_B),
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_BLOCKRAM_SDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_MODE = "FULL";
|
||||
parameter OPTION_WRITE_MODE = "READ_FIRST";
|
||||
|
||||
parameter PORT_W_WIDTH = 1;
|
||||
parameter PORT_W_WR_EN_WIDTH = 1;
|
||||
parameter PORT_W_USED = 1;
|
||||
|
||||
parameter PORT_R_WIDTH = 1;
|
||||
parameter PORT_R_USED = 0;
|
||||
parameter PORT_R_RD_INIT_VALUE = 0;
|
||||
parameter PORT_R_RD_SRST_VALUE = 0;
|
||||
|
||||
input PORT_W_CLK;
|
||||
input PORT_W_CLK_EN;
|
||||
input [15:0] PORT_W_ADDR;
|
||||
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
|
||||
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
|
||||
|
||||
input PORT_R_CLK;
|
||||
input PORT_R_CLK_EN;
|
||||
input [15:0] PORT_R_ADDR;
|
||||
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
|
||||
input PORT_R_RD_SRST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_COMMON \
|
||||
.DO_REG(0), \
|
||||
.INIT(ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)), \
|
||||
.SRVAL(ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
|
||||
|
||||
`define PORTS_COMMON \
|
||||
.DO(DO), \
|
||||
.DOP(DOP), \
|
||||
.DI(DI), \
|
||||
.DIP(DIP), \
|
||||
.WRCLK(PORT_W_CLK), \
|
||||
.RDCLK(PORT_R_CLK), \
|
||||
.WREN(PORT_W_CLK_EN), \
|
||||
.RDEN(PORT_R_CLK_EN), \
|
||||
.REGCE(1'b0), \
|
||||
.SSR(PORT_R_RD_SRST), \
|
||||
.WE(PORT_W_WR_EN),
|
||||
|
||||
`MAKE_DI(DI, DIP, PORT_W_WR_DATA)
|
||||
`MAKE_DO(DO, DOP, PORT_R_RD_DATA)
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_MODE == "HALF") begin
|
||||
RAMB18SDP #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_INITP_18
|
||||
`PARAMS_COMMON
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.WRADDR(PORT_W_ADDR[13:5]),
|
||||
.RDADDR(PORT_R_ADDR[13:5]),
|
||||
);
|
||||
end else if (OPTION_MODE == "FULL") begin
|
||||
RAMB36SDP #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_INITP_36
|
||||
`PARAMS_COMMON
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.WRADDR(PORT_W_ADDR[14:6]),
|
||||
.RDADDR(PORT_R_ADDR[14:6]),
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,284 @@
|
|||
module $__XILINX_BLOCKRAM_TDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_MODE = "FULL";
|
||||
parameter OPTION_HAS_RDFIRST = 0;
|
||||
|
||||
parameter PORT_A_RD_WIDTH = 1;
|
||||
parameter PORT_A_WR_WIDTH = 1;
|
||||
parameter PORT_A_WR_EN_WIDTH = 1;
|
||||
parameter PORT_A_RD_USED = 1;
|
||||
parameter PORT_A_WR_USED = 1;
|
||||
parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_A_RD_INIT_VALUE = 0;
|
||||
parameter PORT_A_RD_SRST_VALUE = 1;
|
||||
|
||||
parameter PORT_B_RD_WIDTH = 1;
|
||||
parameter PORT_B_WR_WIDTH = 1;
|
||||
parameter PORT_B_WR_EN_WIDTH = 1;
|
||||
parameter PORT_B_RD_USED = 0;
|
||||
parameter PORT_B_WR_USED = 0;
|
||||
parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_B_RD_INIT_VALUE = 0;
|
||||
parameter PORT_B_RD_SRST_VALUE = 0;
|
||||
|
||||
input CLK_C;
|
||||
|
||||
input PORT_A_CLK;
|
||||
input PORT_A_CLK_EN;
|
||||
input [15:0] PORT_A_ADDR;
|
||||
input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;
|
||||
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
|
||||
output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;
|
||||
input PORT_A_RD_SRST;
|
||||
|
||||
input PORT_B_CLK;
|
||||
input PORT_B_CLK_EN;
|
||||
input [15:0] PORT_B_ADDR;
|
||||
input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;
|
||||
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
|
||||
output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;
|
||||
input PORT_B_RD_SRST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_COMMON \
|
||||
.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
|
||||
.READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \
|
||||
.READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \
|
||||
.WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \
|
||||
.WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \
|
||||
.DOA_REG(0), \
|
||||
.DOB_REG(0), \
|
||||
.INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \
|
||||
.INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \
|
||||
.SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \
|
||||
.SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)), \
|
||||
.RAM_MODE("TDP"),
|
||||
|
||||
`define PORTS_COMMON \
|
||||
.DOADO(DO_A), \
|
||||
.DOPADOP(DOP_A), \
|
||||
.DIADI(DI_A), \
|
||||
.DIPADIP(DIP_A), \
|
||||
.DOBDO(DO_B), \
|
||||
.DOPBDOP(DOP_B), \
|
||||
.DIBDI(DI_B), \
|
||||
.DIPBDIP(DIP_B), \
|
||||
.CLKARDCLK(PORT_A_CLK), \
|
||||
.CLKBWRCLK(PORT_B_CLK), \
|
||||
.ENARDEN(PORT_A_CLK_EN), \
|
||||
.ENBWREN(PORT_B_CLK_EN), \
|
||||
.REGCEAREGCE(1'b0), \
|
||||
.REGCEB(1'b0), \
|
||||
.RSTRAMARSTRAM(PORT_A_RD_SRST), \
|
||||
.RSTRAMB(PORT_B_RD_SRST), \
|
||||
.RSTREGARSTREG(1'b0), \
|
||||
.RSTREGB(1'b0), \
|
||||
.WEA(WE_A), \
|
||||
.WEBWE(WE_B),
|
||||
|
||||
`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
|
||||
`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
|
||||
`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
|
||||
`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
|
||||
|
||||
wire [3:0] WE_A = {4{PORT_A_WR_EN}};
|
||||
wire [3:0] WE_B = {4{PORT_B_WR_EN}};
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_MODE == "HALF") begin
|
||||
RAMB18E1 #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_INITP_18
|
||||
`PARAMS_COMMON
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.ADDRARDADDR(PORT_A_ADDR[13:0]),
|
||||
.ADDRBWRADDR(PORT_B_ADDR[13:0]),
|
||||
);
|
||||
end else if (OPTION_MODE == "FULL") begin
|
||||
RAMB36E1 #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_INITP_36
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("NONE"),
|
||||
.RAM_EXTENSION_B("NONE"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.ADDRARDADDR({1'b1, PORT_A_ADDR[14:0]}),
|
||||
.ADDRBWRADDR({1'b1, PORT_B_ADDR[14:0]}),
|
||||
);
|
||||
end else begin
|
||||
wire CAS_A, CAS_B;
|
||||
RAMB36E1 #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("LOWER"),
|
||||
.RAM_EXTENSION_B("LOWER"),
|
||||
) lower (
|
||||
.DIADI(DI_A),
|
||||
.DIBDI(DI_B),
|
||||
.CLKARDCLK(PORT_A_CLK),
|
||||
.CLKBWRCLK(PORT_B_CLK),
|
||||
.ENARDEN(PORT_A_CLK_EN),
|
||||
.ENBWREN(PORT_B_CLK_EN),
|
||||
.REGCEAREGCE(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.RSTRAMARSTRAM(PORT_A_RD_SRST),
|
||||
.RSTRAMB(PORT_B_RD_SRST),
|
||||
.RSTREGARSTREG(1'b0),
|
||||
.RSTREGB(1'b0),
|
||||
.WEA(WE_A),
|
||||
.WEBWE(WE_B),
|
||||
.ADDRARDADDR(PORT_A_ADDR),
|
||||
.ADDRBWRADDR(PORT_B_ADDR),
|
||||
.CASCADEOUTA(CAS_A),
|
||||
.CASCADEOUTB(CAS_B),
|
||||
);
|
||||
RAMB36E1 #(
|
||||
`PARAMS_INIT_36_U
|
||||
`PARAMS_COMMON
|
||||
.RAM_EXTENSION_A("UPPER"),
|
||||
.RAM_EXTENSION_B("UPPER"),
|
||||
) upper (
|
||||
.DOADO(DO_A),
|
||||
.DIADI(DI_A),
|
||||
.DOBDO(DO_B),
|
||||
.DIBDI(DI_B),
|
||||
.CLKARDCLK(PORT_A_CLK),
|
||||
.CLKBWRCLK(PORT_B_CLK),
|
||||
.ENARDEN(PORT_A_CLK_EN),
|
||||
.ENBWREN(PORT_B_CLK_EN),
|
||||
.REGCEAREGCE(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.RSTRAMARSTRAM(PORT_A_RD_SRST),
|
||||
.RSTRAMB(PORT_B_RD_SRST),
|
||||
.RSTREGARSTREG(1'b0),
|
||||
.RSTREGB(1'b0),
|
||||
.WEA(WE_A),
|
||||
.WEBWE(WE_B),
|
||||
.ADDRARDADDR(PORT_A_ADDR),
|
||||
.ADDRBWRADDR(PORT_B_ADDR),
|
||||
.CASCADEINA(CAS_A),
|
||||
.CASCADEINB(CAS_B),
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_BLOCKRAM_SDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_MODE = "FULL";
|
||||
parameter OPTION_WRITE_MODE = "READ_FIRST";
|
||||
|
||||
parameter PORT_W_WIDTH = 1;
|
||||
parameter PORT_W_WR_EN_WIDTH = 1;
|
||||
parameter PORT_W_USED = 1;
|
||||
|
||||
parameter PORT_R_WIDTH = 1;
|
||||
parameter PORT_R_USED = 0;
|
||||
parameter PORT_R_RD_INIT_VALUE = 0;
|
||||
parameter PORT_R_RD_SRST_VALUE = 0;
|
||||
|
||||
input CLK_C;
|
||||
|
||||
input PORT_W_CLK;
|
||||
input PORT_W_CLK_EN;
|
||||
input [15:0] PORT_W_ADDR;
|
||||
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
|
||||
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
|
||||
|
||||
input PORT_R_CLK;
|
||||
input PORT_R_CLK_EN;
|
||||
input [15:0] PORT_R_ADDR;
|
||||
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
|
||||
input PORT_R_RD_SRST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_COMMON \
|
||||
.WRITE_MODE_A(OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(OPTION_WRITE_MODE), \
|
||||
.READ_WIDTH_A(PORT_R_USED ? PORT_R_WIDTH : 0), \
|
||||
.READ_WIDTH_B(0), \
|
||||
.WRITE_WIDTH_A(0), \
|
||||
.WRITE_WIDTH_B(PORT_W_USED ? PORT_W_WIDTH : 0), \
|
||||
.DOA_REG(0), \
|
||||
.DOB_REG(0), \
|
||||
.RAM_MODE("SDP"),
|
||||
|
||||
`define PORTS_COMMON \
|
||||
.CLKBWRCLK(PORT_W_CLK), \
|
||||
.CLKARDCLK(PORT_R_CLK), \
|
||||
.ENBWREN(PORT_W_CLK_EN), \
|
||||
.ENARDEN(PORT_R_CLK_EN), \
|
||||
.REGCEAREGCE(1'b0), \
|
||||
.REGCEB(1'b0), \
|
||||
.RSTRAMARSTRAM(PORT_R_RD_SRST), \
|
||||
.RSTRAMB(1'b0), \
|
||||
.RSTREGARSTREG(1'b0), \
|
||||
.RSTREGB(1'b0), \
|
||||
.WEA(0), \
|
||||
.WEBWE(PORT_W_WR_EN),
|
||||
|
||||
`MAKE_DI(DI, DIP, PORT_W_WR_DATA)
|
||||
`MAKE_DO(DO, DOP, PORT_R_RD_DATA)
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_MODE == "HALF") begin
|
||||
RAMB18E1 #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_INITP_18
|
||||
`PARAMS_COMMON
|
||||
.INIT_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),
|
||||
.INIT_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[35:18]) : 0),
|
||||
.SRVAL_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
|
||||
.SRVAL_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[35:18]) : 0),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.ADDRARDADDR(PORT_R_ADDR[13:0]),
|
||||
.ADDRBWRADDR(PORT_W_ADDR[13:0]),
|
||||
.DOADO(DO[15:0]),
|
||||
.DOBDO(DO[31:16]),
|
||||
.DOPADOP(DOP[1:0]),
|
||||
.DOPBDOP(DOP[3:2]),
|
||||
.DIADI(DI[15:0]),
|
||||
.DIBDI(PORT_W_WIDTH == 36 ? DI[31:16] : DI[15:0]),
|
||||
.DIPADIP(DIP[1:0]),
|
||||
.DIPBDIP(PORT_W_WIDTH == 36 ? DIP[3:2] : DIP[1:0]),
|
||||
);
|
||||
end else if (OPTION_MODE == "FULL") begin
|
||||
RAMB36E1 #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_INITP_36
|
||||
`PARAMS_COMMON
|
||||
.INIT_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),
|
||||
.INIT_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[71:36]) : 0),
|
||||
.SRVAL_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
|
||||
.SRVAL_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[71:36]) : 0),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.ADDRARDADDR({1'b1, PORT_R_ADDR}),
|
||||
.ADDRBWRADDR({1'b1, PORT_W_ADDR}),
|
||||
.DOADO(DO[31:0]),
|
||||
.DOBDO(DO[63:32]),
|
||||
.DOPADOP(DOP[3:0]),
|
||||
.DOPBDOP(DOP[7:4]),
|
||||
.DIADI(DI[31:0]),
|
||||
.DIBDI(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),
|
||||
.DIPADIP(DIP[3:0]),
|
||||
.DIPBDIP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
module $__XILINX_BLOCKRAM_TDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_MODE = "FULL";
|
||||
parameter OPTION_HAS_RDFIRST = 0;
|
||||
|
||||
parameter PORT_A_RD_WIDTH = 1;
|
||||
parameter PORT_A_WR_WIDTH = 1;
|
||||
parameter PORT_A_WR_EN_WIDTH = 1;
|
||||
parameter PORT_A_RD_USED = 1;
|
||||
parameter PORT_A_WR_USED = 1;
|
||||
parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_A_RD_INIT_VALUE = 0;
|
||||
parameter PORT_A_RD_SRST_VALUE = 1;
|
||||
|
||||
parameter PORT_B_RD_WIDTH = 1;
|
||||
parameter PORT_B_WR_WIDTH = 1;
|
||||
parameter PORT_B_WR_EN_WIDTH = 1;
|
||||
parameter PORT_B_RD_USED = 0;
|
||||
parameter PORT_B_WR_USED = 0;
|
||||
parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
|
||||
parameter PORT_B_RD_INIT_VALUE = 0;
|
||||
parameter PORT_B_RD_SRST_VALUE = 0;
|
||||
|
||||
input PORT_A_CLK;
|
||||
input PORT_A_CLK_EN;
|
||||
input [15:0] PORT_A_ADDR;
|
||||
input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;
|
||||
input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
|
||||
output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;
|
||||
input PORT_A_RD_SRST;
|
||||
|
||||
input PORT_B_CLK;
|
||||
input PORT_B_CLK_EN;
|
||||
input [15:0] PORT_B_ADDR;
|
||||
input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;
|
||||
input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
|
||||
output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;
|
||||
input PORT_B_RD_SRST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_COMMON \
|
||||
.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
|
||||
.READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \
|
||||
.READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \
|
||||
.WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \
|
||||
.WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \
|
||||
.DOA_REG(0), \
|
||||
.DOB_REG(0), \
|
||||
.INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \
|
||||
.INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \
|
||||
.SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \
|
||||
.SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)),
|
||||
|
||||
`define PORTS_COMMON \
|
||||
.DOUTADOUT(DO_A), \
|
||||
.DOUTPADOUTP(DOP_A), \
|
||||
.DINADIN(DI_A), \
|
||||
.DINPADINP(DIP_A), \
|
||||
.DOUTBDOUT(DO_B), \
|
||||
.DOUTPBDOUTP(DOP_B), \
|
||||
.DINBDIN(DI_B), \
|
||||
.DINPBDINP(DIP_B), \
|
||||
.CLKARDCLK(PORT_A_CLK), \
|
||||
.CLKBWRCLK(PORT_B_CLK), \
|
||||
.ENARDEN(PORT_A_CLK_EN), \
|
||||
.ENBWREN(PORT_B_CLK_EN), \
|
||||
.REGCEAREGCE(1'b0), \
|
||||
.REGCEB(1'b0), \
|
||||
.ADDRENA(1'b1), \
|
||||
.ADDRENB(1'b1), \
|
||||
.RSTRAMARSTRAM(PORT_A_RD_SRST), \
|
||||
.RSTRAMB(PORT_B_RD_SRST), \
|
||||
.RSTREGARSTREG(1'b0), \
|
||||
.RSTREGB(1'b0), \
|
||||
.WEA(WE_A), \
|
||||
.WEBWE(WE_B), \
|
||||
.ADDRARDADDR(PORT_A_ADDR), \
|
||||
.ADDRBWRADDR(PORT_B_ADDR), \
|
||||
.SLEEP(1'b0),
|
||||
|
||||
`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
|
||||
`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
|
||||
`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
|
||||
`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
|
||||
|
||||
wire [3:0] WE_A = {4{PORT_A_WR_EN}};
|
||||
wire [3:0] WE_B = {4{PORT_B_WR_EN}};
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_MODE == "HALF") begin
|
||||
RAMB18E2 #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_INITP_18
|
||||
`PARAMS_COMMON
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
);
|
||||
end else if (OPTION_MODE == "FULL") begin
|
||||
RAMB36E2 #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_INITP_36
|
||||
`PARAMS_COMMON
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_BLOCKRAM_SDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_MODE = "FULL";
|
||||
parameter OPTION_WRITE_MODE = "READ_FIRST";
|
||||
|
||||
parameter PORT_W_WIDTH = 1;
|
||||
parameter PORT_W_WR_EN_WIDTH = 1;
|
||||
parameter PORT_W_USED = 1;
|
||||
|
||||
parameter PORT_R_WIDTH = 1;
|
||||
parameter PORT_R_USED = 0;
|
||||
parameter PORT_R_RD_INIT_VALUE = 0;
|
||||
parameter PORT_R_RD_SRST_VALUE = 0;
|
||||
|
||||
input PORT_W_CLK;
|
||||
input PORT_W_CLK_EN;
|
||||
input [15:0] PORT_W_ADDR;
|
||||
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
|
||||
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
|
||||
|
||||
input PORT_R_CLK;
|
||||
input PORT_R_CLK_EN;
|
||||
input [15:0] PORT_R_ADDR;
|
||||
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
|
||||
input PORT_R_RD_SRST;
|
||||
|
||||
`include "brams_defs.vh"
|
||||
|
||||
`define PARAMS_COMMON \
|
||||
.WRITE_MODE_A(OPTION_WRITE_MODE), \
|
||||
.WRITE_MODE_B(OPTION_WRITE_MODE), \
|
||||
.READ_WIDTH_A(PORT_R_USED ? PORT_R_WIDTH : 0), \
|
||||
.READ_WIDTH_B(0), \
|
||||
.WRITE_WIDTH_A(0), \
|
||||
.WRITE_WIDTH_B(PORT_W_USED ? PORT_W_WIDTH : 0), \
|
||||
.DOA_REG(0), \
|
||||
.DOB_REG(0),
|
||||
|
||||
`define PORTS_COMMON \
|
||||
.CLKBWRCLK(PORT_W_CLK), \
|
||||
.CLKARDCLK(PORT_R_CLK), \
|
||||
.ENBWREN(PORT_W_CLK_EN), \
|
||||
.ENARDEN(PORT_R_CLK_EN), \
|
||||
.REGCEAREGCE(1'b0), \
|
||||
.REGCEB(1'b0), \
|
||||
.ADDRENA(1'b1), \
|
||||
.ADDRENB(1'b1), \
|
||||
.RSTRAMARSTRAM(PORT_R_RD_SRST), \
|
||||
.RSTRAMB(1'b0), \
|
||||
.RSTREGARSTREG(1'b0), \
|
||||
.RSTREGB(1'b0), \
|
||||
.WEA(0), \
|
||||
.WEBWE(PORT_W_WR_EN), \
|
||||
.ADDRARDADDR(PORT_R_ADDR), \
|
||||
.ADDRBWRADDR(PORT_W_ADDR), \
|
||||
.SLEEP(1'b0),
|
||||
|
||||
`MAKE_DI(DI, DIP, PORT_W_WR_DATA)
|
||||
`MAKE_DO(DO, DOP, PORT_R_RD_DATA)
|
||||
|
||||
generate
|
||||
|
||||
if (OPTION_MODE == "HALF") begin
|
||||
RAMB18E2 #(
|
||||
`PARAMS_INIT_18
|
||||
`PARAMS_INITP_18
|
||||
`PARAMS_COMMON
|
||||
.INIT_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),
|
||||
.INIT_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_INIT_VALUE[35:18]) : 0),
|
||||
.SRVAL_A(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[17:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
|
||||
.SRVAL_B(PORT_R_WIDTH == 36 ? ival(18, PORT_R_RD_SRST_VALUE[35:18]) : 0),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.DOUTADOUT(DO[15:0]),
|
||||
.DOUTBDOUT(DO[31:16]),
|
||||
.DOUTPADOUTP(DOP[1:0]),
|
||||
.DOUTPBDOUTP(DOP[3:2]),
|
||||
.DINADIN(DI[15:0]),
|
||||
.DINBDIN(PORT_W_WIDTH == 36 ? DI[31:16] : DI[15:0]),
|
||||
.DINPADINP(DIP[1:0]),
|
||||
.DINPBDINP(PORT_W_WIDTH == 36 ? DIP[3:2] : DIP[1:0]),
|
||||
);
|
||||
end else if (OPTION_MODE == "FULL") begin
|
||||
RAMB36E2 #(
|
||||
`PARAMS_INIT_36
|
||||
`PARAMS_INITP_36
|
||||
`PARAMS_COMMON
|
||||
.INIT_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_INIT_VALUE)),
|
||||
.INIT_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_INIT_VALUE[71:36]) : 0),
|
||||
.SRVAL_A(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[35:0]) : ival(PORT_R_WIDTH, PORT_R_RD_SRST_VALUE)),
|
||||
.SRVAL_B(PORT_R_WIDTH == 72 ? ival(36, PORT_R_RD_SRST_VALUE[71:36]) : 0),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_COMMON
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTBDOUT(DO[63:32]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.DOUTPBDOUTP(DOP[7:4]),
|
||||
.DINADIN(DI[31:0]),
|
||||
.DINBDIN(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),
|
||||
.DINPADINP(DIP[3:0]),
|
||||
.DINPBDINP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# Block RAMs for the original Virtex.
|
||||
# The corresponding mapping file is brams_xcv_map.v
|
||||
|
||||
ram block $__XILINX_BLOCKRAM_ {
|
||||
abits 12;
|
||||
widths 1 2 4 8 16 per_port;
|
||||
cost 32;
|
||||
init any;
|
||||
port srsw "A" "B" {
|
||||
clock posedge;
|
||||
clken;
|
||||
rdwr new;
|
||||
rdinit zero;
|
||||
rdsrst zero gated_clken;
|
||||
optional;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
module $__XILINX_BLOCKRAM_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
|
||||
parameter PORT_A_WIDTH = 1;
|
||||
parameter PORT_B_WIDTH = 1;
|
||||
parameter PORT_A_USED = 1;
|
||||
parameter PORT_B_USED = 0;
|
||||
|
||||
input PORT_A_CLK;
|
||||
input PORT_A_CLK_EN;
|
||||
input [11:0] PORT_A_ADDR;
|
||||
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
|
||||
input PORT_A_WR_EN;
|
||||
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
|
||||
input PORT_A_RD_SRST;
|
||||
|
||||
input PORT_B_CLK;
|
||||
input PORT_B_CLK_EN;
|
||||
input [11:0] PORT_B_ADDR;
|
||||
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
|
||||
input PORT_B_WR_EN;
|
||||
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
|
||||
input PORT_B_RD_SRST;
|
||||
|
||||
`define PARAMS_INIT \
|
||||
.INIT_00(INIT[0*256+:256]), \
|
||||
.INIT_01(INIT[1*256+:256]), \
|
||||
.INIT_02(INIT[2*256+:256]), \
|
||||
.INIT_03(INIT[3*256+:256]), \
|
||||
.INIT_04(INIT[4*256+:256]), \
|
||||
.INIT_05(INIT[5*256+:256]), \
|
||||
.INIT_06(INIT[6*256+:256]), \
|
||||
.INIT_07(INIT[7*256+:256]), \
|
||||
.INIT_08(INIT[8*256+:256]), \
|
||||
.INIT_09(INIT[9*256+:256]), \
|
||||
.INIT_0A(INIT[10*256+:256]), \
|
||||
.INIT_0B(INIT[11*256+:256]), \
|
||||
.INIT_0C(INIT[12*256+:256]), \
|
||||
.INIT_0D(INIT[13*256+:256]), \
|
||||
.INIT_0E(INIT[14*256+:256]), \
|
||||
.INIT_0F(INIT[15*256+:256]),
|
||||
|
||||
`define PORTS_DP(addr_slice_a, addr_slice_b) \
|
||||
.CLKA(PORT_A_CLK), \
|
||||
.ENA(PORT_A_CLK_EN), \
|
||||
.WEA(PORT_A_WR_EN), \
|
||||
.RSTA(PORT_A_RD_SRST), \
|
||||
.ADDRA(PORT_A_ADDR addr_slice_a), \
|
||||
.DOA(PORT_A_RD_DATA), \
|
||||
.DIA(PORT_A_WR_DATA), \
|
||||
.CLKB(PORT_B_CLK), \
|
||||
.ENB(PORT_B_CLK_EN), \
|
||||
.WEB(PORT_B_WR_EN), \
|
||||
.RSTB(PORT_B_RD_SRST), \
|
||||
.ADDRB(PORT_B_ADDR addr_slice_b), \
|
||||
.DOB(PORT_B_RD_DATA), \
|
||||
.DIB(PORT_B_WR_DATA),
|
||||
|
||||
`define PORTS_DP_SWAP(addr_slice_a, addr_slice_b) \
|
||||
.CLKB(PORT_A_CLK), \
|
||||
.ENB(PORT_A_CLK_EN), \
|
||||
.WEB(PORT_A_WR_EN), \
|
||||
.RSTB(PORT_A_RD_SRST), \
|
||||
.ADDRB(PORT_A_ADDR addr_slice_a), \
|
||||
.DOB(PORT_A_RD_DATA), \
|
||||
.DIB(PORT_A_WR_DATA), \
|
||||
.CLKA(PORT_B_CLK), \
|
||||
.ENA(PORT_B_CLK_EN), \
|
||||
.WEA(PORT_B_WR_EN), \
|
||||
.RSTA(PORT_B_RD_SRST), \
|
||||
.ADDRA(PORT_B_ADDR addr_slice_b), \
|
||||
.DOA(PORT_B_RD_DATA), \
|
||||
.DIA(PORT_B_WR_DATA),
|
||||
|
||||
`define PORTS_SP(addr_slice) \
|
||||
.CLK(PORT_A_CLK), \
|
||||
.EN(PORT_A_CLK_EN), \
|
||||
.WE(PORT_A_WR_EN), \
|
||||
.RST(PORT_A_RD_SRST), \
|
||||
.ADDR(PORT_A_ADDR addr_slice), \
|
||||
.DO(PORT_A_RD_DATA), \
|
||||
.DI(PORT_A_WR_DATA),
|
||||
|
||||
generate
|
||||
|
||||
if (!PORT_B_USED) begin
|
||||
case (PORT_A_WIDTH)
|
||||
1: RAMB4_S1 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([11:0])
|
||||
);
|
||||
2: RAMB4_S2 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([11:1])
|
||||
);
|
||||
4: RAMB4_S4 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([11:2])
|
||||
);
|
||||
8: RAMB4_S8 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([11:3])
|
||||
);
|
||||
16: RAMB4_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_SP([11:4])
|
||||
);
|
||||
endcase
|
||||
end else begin
|
||||
case (PORT_A_WIDTH)
|
||||
1: case(PORT_B_WIDTH)
|
||||
1: RAMB4_S1_S1 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:0], [11:0])
|
||||
);
|
||||
2: RAMB4_S1_S2 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:0], [11:1])
|
||||
);
|
||||
4: RAMB4_S1_S4 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:0], [11:2])
|
||||
);
|
||||
8: RAMB4_S1_S8 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:0], [11:3])
|
||||
);
|
||||
16: RAMB4_S1_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:0], [11:4])
|
||||
);
|
||||
endcase
|
||||
2: case(PORT_B_WIDTH)
|
||||
1: RAMB4_S1_S2 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:1], [11:0])
|
||||
);
|
||||
2: RAMB4_S2_S2 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:1], [11:1])
|
||||
);
|
||||
4: RAMB4_S2_S4 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:1], [11:2])
|
||||
);
|
||||
8: RAMB4_S2_S8 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:1], [11:3])
|
||||
);
|
||||
16: RAMB4_S2_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:1], [11:4])
|
||||
);
|
||||
endcase
|
||||
4: case(PORT_B_WIDTH)
|
||||
1: RAMB4_S1_S4 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:2], [11:0])
|
||||
);
|
||||
2: RAMB4_S2_S4 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:2], [11:1])
|
||||
);
|
||||
4: RAMB4_S4_S4 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:2], [11:2])
|
||||
);
|
||||
8: RAMB4_S4_S8 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:2], [11:3])
|
||||
);
|
||||
16: RAMB4_S4_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:2], [11:4])
|
||||
);
|
||||
endcase
|
||||
8: case(PORT_B_WIDTH)
|
||||
1: RAMB4_S1_S8 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:3], [11:0])
|
||||
);
|
||||
2: RAMB4_S2_S8 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:3], [11:1])
|
||||
);
|
||||
4: RAMB4_S4_S8 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:3], [11:2])
|
||||
);
|
||||
8: RAMB4_S8_S8 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:3], [11:3])
|
||||
);
|
||||
16: RAMB4_S8_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:3], [11:4])
|
||||
);
|
||||
endcase
|
||||
16: case(PORT_B_WIDTH)
|
||||
1: RAMB4_S1_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:4], [11:0])
|
||||
);
|
||||
2: RAMB4_S2_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:4], [11:1])
|
||||
);
|
||||
4: RAMB4_S4_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:4], [11:2])
|
||||
);
|
||||
8: RAMB4_S8_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP_SWAP([11:4], [11:3])
|
||||
);
|
||||
16: RAMB4_S16_S16 #(
|
||||
`PARAMS_INIT
|
||||
) _TECHMAP_REPLACE_ (
|
||||
`PORTS_DP([11:4], [11:4])
|
||||
);
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
bram $__XILINX_RAM16X1D
|
||||
init 1
|
||||
abits 4
|
||||
dbits 1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 0
|
||||
clocks 0 1
|
||||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
|
||||
match $__XILINX_RAM16X1D
|
||||
min bits 2
|
||||
min wports 1
|
||||
make_outreg
|
||||
endmatch
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
bram $__XILINX_RAM32X1D
|
||||
init 1
|
||||
abits 5
|
||||
dbits 1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 0
|
||||
clocks 0 1
|
||||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAM64X1D
|
||||
init 1
|
||||
abits 6
|
||||
dbits 1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 0
|
||||
clocks 0 1
|
||||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAM128X1D
|
||||
init 1
|
||||
abits 7
|
||||
dbits 1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 0
|
||||
clocks 0 1
|
||||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
|
||||
bram $__XILINX_RAM32X6SDP
|
||||
init 1
|
||||
abits 5
|
||||
dbits 6
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 0
|
||||
clocks 0 1
|
||||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAM64X3SDP
|
||||
init 1
|
||||
abits 6
|
||||
dbits 3
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 0
|
||||
clocks 0 1
|
||||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAM32X2Q
|
||||
init 1
|
||||
abits 5
|
||||
dbits 2
|
||||
groups 2
|
||||
ports 3 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 0
|
||||
clocks 0 1
|
||||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAM64X1Q
|
||||
init 1
|
||||
abits 6
|
||||
dbits 1
|
||||
groups 2
|
||||
ports 3 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 0
|
||||
clocks 0 1
|
||||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
|
||||
match $__XILINX_RAM32X1D
|
||||
min bits 3
|
||||
min wports 1
|
||||
make_outreg
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAM64X1D
|
||||
min bits 5
|
||||
min wports 1
|
||||
make_outreg
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAM128X1D
|
||||
min bits 9
|
||||
min wports 1
|
||||
make_outreg
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
|
||||
match $__XILINX_RAM32X6SDP
|
||||
min bits 5
|
||||
min wports 1
|
||||
make_outreg
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAM64X3SDP
|
||||
min bits 6
|
||||
min wports 1
|
||||
make_outreg
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAM32X2Q
|
||||
min bits 5
|
||||
min rports 2
|
||||
min wports 1
|
||||
make_outreg
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAM64X1Q
|
||||
min bits 5
|
||||
min rports 2
|
||||
min wports 1
|
||||
make_outreg
|
||||
endmatch
|
||||
|
|
@ -1,279 +0,0 @@
|
|||
|
||||
module \$__XILINX_RAM16X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [15:0] INIT = 16'bx;
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
|
||||
input [3:0] A1ADDR;
|
||||
output A1DATA;
|
||||
|
||||
input [3:0] B1ADDR;
|
||||
input B1DATA;
|
||||
input B1EN;
|
||||
|
||||
RAM16X1D #(
|
||||
.INIT(INIT),
|
||||
.IS_WCLK_INVERTED(!CLKPOL2)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPRA0(A1ADDR[0]),
|
||||
.DPRA1(A1ADDR[1]),
|
||||
.DPRA2(A1ADDR[2]),
|
||||
.DPRA3(A1ADDR[3]),
|
||||
.DPO(A1DATA),
|
||||
|
||||
.A0(B1ADDR[0]),
|
||||
.A1(B1ADDR[1]),
|
||||
.A2(B1ADDR[2]),
|
||||
.A3(B1ADDR[3]),
|
||||
.D(B1DATA),
|
||||
.WCLK(CLK1),
|
||||
.WE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [31:0] INIT = 32'bx;
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
|
||||
input [4:0] A1ADDR;
|
||||
output A1DATA;
|
||||
|
||||
input [4:0] B1ADDR;
|
||||
input B1DATA;
|
||||
input B1EN;
|
||||
|
||||
RAM32X1D #(
|
||||
.INIT(INIT),
|
||||
.IS_WCLK_INVERTED(!CLKPOL2)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPRA0(A1ADDR[0]),
|
||||
.DPRA1(A1ADDR[1]),
|
||||
.DPRA2(A1ADDR[2]),
|
||||
.DPRA3(A1ADDR[3]),
|
||||
.DPRA4(A1ADDR[4]),
|
||||
.DPO(A1DATA),
|
||||
|
||||
.A0(B1ADDR[0]),
|
||||
.A1(B1ADDR[1]),
|
||||
.A2(B1ADDR[2]),
|
||||
.A3(B1ADDR[3]),
|
||||
.A4(B1ADDR[4]),
|
||||
.D(B1DATA),
|
||||
.WCLK(CLK1),
|
||||
.WE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [63:0] INIT = 64'bx;
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
|
||||
input [5:0] A1ADDR;
|
||||
output A1DATA;
|
||||
|
||||
input [5:0] B1ADDR;
|
||||
input B1DATA;
|
||||
input B1EN;
|
||||
|
||||
RAM64X1D #(
|
||||
.INIT(INIT),
|
||||
.IS_WCLK_INVERTED(!CLKPOL2)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPRA0(A1ADDR[0]),
|
||||
.DPRA1(A1ADDR[1]),
|
||||
.DPRA2(A1ADDR[2]),
|
||||
.DPRA3(A1ADDR[3]),
|
||||
.DPRA4(A1ADDR[4]),
|
||||
.DPRA5(A1ADDR[5]),
|
||||
.DPO(A1DATA),
|
||||
|
||||
.A0(B1ADDR[0]),
|
||||
.A1(B1ADDR[1]),
|
||||
.A2(B1ADDR[2]),
|
||||
.A3(B1ADDR[3]),
|
||||
.A4(B1ADDR[4]),
|
||||
.A5(B1ADDR[5]),
|
||||
.D(B1DATA),
|
||||
.WCLK(CLK1),
|
||||
.WE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [127:0] INIT = 128'bx;
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
|
||||
input [6:0] A1ADDR;
|
||||
output A1DATA;
|
||||
|
||||
input [6:0] B1ADDR;
|
||||
input B1DATA;
|
||||
input B1EN;
|
||||
|
||||
RAM128X1D #(
|
||||
.INIT(INIT),
|
||||
.IS_WCLK_INVERTED(!CLKPOL2)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPRA(A1ADDR),
|
||||
.DPO(A1DATA),
|
||||
|
||||
.A(B1ADDR),
|
||||
.D(B1DATA),
|
||||
.WCLK(CLK1),
|
||||
.WE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
module \$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [32*6-1:0] INIT = {32*6{1'bx}};
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
|
||||
input [4:0] A1ADDR;
|
||||
output [5:0] A1DATA;
|
||||
|
||||
input [4:0] B1ADDR;
|
||||
input [5:0] B1DATA;
|
||||
input B1EN;
|
||||
|
||||
wire [1:0] DOD_unused;
|
||||
|
||||
RAM32M #(
|
||||
.INIT_A({INIT[187:186], INIT[181:180], INIT[175:174], INIT[169:168], INIT[163:162], INIT[157:156], INIT[151:150], INIT[145:144], INIT[139:138], INIT[133:132], INIT[127:126], INIT[121:120], INIT[115:114], INIT[109:108], INIT[103:102], INIT[ 97: 96], INIT[ 91: 90], INIT[ 85: 84], INIT[ 79: 78], INIT[ 73: 72], INIT[ 67: 66], INIT[ 61: 60], INIT[ 55: 54], INIT[ 49: 48], INIT[ 43: 42], INIT[ 37: 36], INIT[ 31: 30], INIT[ 25: 24], INIT[ 19: 18], INIT[ 13: 12], INIT[ 7: 6], INIT[ 1: 0]}),
|
||||
.INIT_B({INIT[189:188], INIT[183:182], INIT[177:176], INIT[171:170], INIT[165:164], INIT[159:158], INIT[153:152], INIT[147:146], INIT[141:140], INIT[135:134], INIT[129:128], INIT[123:122], INIT[117:116], INIT[111:110], INIT[105:104], INIT[ 99: 98], INIT[ 93: 92], INIT[ 87: 86], INIT[ 81: 80], INIT[ 75: 74], INIT[ 69: 68], INIT[ 63: 62], INIT[ 57: 56], INIT[ 51: 50], INIT[ 45: 44], INIT[ 39: 38], INIT[ 33: 32], INIT[ 27: 26], INIT[ 21: 20], INIT[ 15: 14], INIT[ 9: 8], INIT[ 3: 2]}),
|
||||
.INIT_C({INIT[191:190], INIT[185:184], INIT[179:178], INIT[173:172], INIT[167:166], INIT[161:160], INIT[155:154], INIT[149:148], INIT[143:142], INIT[137:136], INIT[131:130], INIT[125:124], INIT[119:118], INIT[113:112], INIT[107:106], INIT[101:100], INIT[ 95: 94], INIT[ 89: 88], INIT[ 83: 82], INIT[ 77: 76], INIT[ 71: 70], INIT[ 65: 64], INIT[ 59: 58], INIT[ 53: 52], INIT[ 47: 46], INIT[ 41: 40], INIT[ 35: 34], INIT[ 29: 28], INIT[ 23: 22], INIT[ 17: 16], INIT[ 11: 10], INIT[ 5: 4]}),
|
||||
.INIT_D(64'bx),
|
||||
.IS_WCLK_INVERTED(!CLKPOL2)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ADDRA(A1ADDR),
|
||||
.ADDRB(A1ADDR),
|
||||
.ADDRC(A1ADDR),
|
||||
.DOA(A1DATA[1:0]),
|
||||
.DOB(A1DATA[3:2]),
|
||||
.DOC(A1DATA[5:4]),
|
||||
.DOD(DOD_unused),
|
||||
|
||||
.ADDRD(B1ADDR),
|
||||
.DIA(B1DATA[1:0]),
|
||||
.DIB(B1DATA[3:2]),
|
||||
.DIC(B1DATA[5:4]),
|
||||
.DID(2'b00),
|
||||
.WCLK(CLK1),
|
||||
.WE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [64*3-1:0] INIT = {64*3{1'bx}};
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
|
||||
input [5:0] A1ADDR;
|
||||
output [2:0] A1DATA;
|
||||
|
||||
input [5:0] B1ADDR;
|
||||
input [2:0] B1DATA;
|
||||
input B1EN;
|
||||
|
||||
wire DOD_unused;
|
||||
|
||||
RAM64M #(
|
||||
.INIT_A({INIT[189], INIT[186], INIT[183], INIT[180], INIT[177], INIT[174], INIT[171], INIT[168], INIT[165], INIT[162], INIT[159], INIT[156], INIT[153], INIT[150], INIT[147], INIT[144], INIT[141], INIT[138], INIT[135], INIT[132], INIT[129], INIT[126], INIT[123], INIT[120], INIT[117], INIT[114], INIT[111], INIT[108], INIT[105], INIT[102], INIT[ 99], INIT[ 96], INIT[ 93], INIT[ 90], INIT[ 87], INIT[ 84], INIT[ 81], INIT[ 78], INIT[ 75], INIT[ 72], INIT[ 69], INIT[ 66], INIT[ 63], INIT[ 60], INIT[ 57], INIT[ 54], INIT[ 51], INIT[ 48], INIT[ 45], INIT[ 42], INIT[ 39], INIT[ 36], INIT[ 33], INIT[ 30], INIT[ 27], INIT[ 24], INIT[ 21], INIT[ 18], INIT[ 15], INIT[ 12], INIT[ 9], INIT[ 6], INIT[ 3], INIT[ 0]}),
|
||||
.INIT_B({INIT[190], INIT[187], INIT[184], INIT[181], INIT[178], INIT[175], INIT[172], INIT[169], INIT[166], INIT[163], INIT[160], INIT[157], INIT[154], INIT[151], INIT[148], INIT[145], INIT[142], INIT[139], INIT[136], INIT[133], INIT[130], INIT[127], INIT[124], INIT[121], INIT[118], INIT[115], INIT[112], INIT[109], INIT[106], INIT[103], INIT[100], INIT[ 97], INIT[ 94], INIT[ 91], INIT[ 88], INIT[ 85], INIT[ 82], INIT[ 79], INIT[ 76], INIT[ 73], INIT[ 70], INIT[ 67], INIT[ 64], INIT[ 61], INIT[ 58], INIT[ 55], INIT[ 52], INIT[ 49], INIT[ 46], INIT[ 43], INIT[ 40], INIT[ 37], INIT[ 34], INIT[ 31], INIT[ 28], INIT[ 25], INIT[ 22], INIT[ 19], INIT[ 16], INIT[ 13], INIT[ 10], INIT[ 7], INIT[ 4], INIT[ 1]}),
|
||||
.INIT_C({INIT[191], INIT[188], INIT[185], INIT[182], INIT[179], INIT[176], INIT[173], INIT[170], INIT[167], INIT[164], INIT[161], INIT[158], INIT[155], INIT[152], INIT[149], INIT[146], INIT[143], INIT[140], INIT[137], INIT[134], INIT[131], INIT[128], INIT[125], INIT[122], INIT[119], INIT[116], INIT[113], INIT[110], INIT[107], INIT[104], INIT[101], INIT[ 98], INIT[ 95], INIT[ 92], INIT[ 89], INIT[ 86], INIT[ 83], INIT[ 80], INIT[ 77], INIT[ 74], INIT[ 71], INIT[ 68], INIT[ 65], INIT[ 62], INIT[ 59], INIT[ 56], INIT[ 53], INIT[ 50], INIT[ 47], INIT[ 44], INIT[ 41], INIT[ 38], INIT[ 35], INIT[ 32], INIT[ 29], INIT[ 26], INIT[ 23], INIT[ 20], INIT[ 17], INIT[ 14], INIT[ 11], INIT[ 8], INIT[ 5], INIT[ 2]}),
|
||||
.INIT_D(64'bx),
|
||||
.IS_WCLK_INVERTED(!CLKPOL2)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ADDRA(A1ADDR),
|
||||
.ADDRB(A1ADDR),
|
||||
.ADDRC(A1ADDR),
|
||||
.DOA(A1DATA[0]),
|
||||
.DOB(A1DATA[1]),
|
||||
.DOC(A1DATA[2]),
|
||||
.DOD(DOD_unused),
|
||||
|
||||
.ADDRD(B1ADDR),
|
||||
.DIA(B1DATA[0]),
|
||||
.DIB(B1DATA[1]),
|
||||
.DIC(B1DATA[2]),
|
||||
.DID(1'b0),
|
||||
.WCLK(CLK1),
|
||||
.WE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__XILINX_RAM32X2Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [63:0] INIT = 64'bx;
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
|
||||
input [4:0] A1ADDR, A2ADDR, A3ADDR;
|
||||
output [1:0] A1DATA, A2DATA, A3DATA;
|
||||
|
||||
input [4:0] B1ADDR;
|
||||
input [1:0] B1DATA;
|
||||
input B1EN;
|
||||
|
||||
RAM32M #(
|
||||
.INIT_A(INIT),
|
||||
.INIT_B(INIT),
|
||||
.INIT_C(INIT),
|
||||
.INIT_D(INIT),
|
||||
.IS_WCLK_INVERTED(!CLKPOL2)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ADDRA(A1ADDR),
|
||||
.ADDRB(A2ADDR),
|
||||
.ADDRC(A3ADDR),
|
||||
.DOA(A1DATA),
|
||||
.DOB(A2DATA),
|
||||
.DOC(A3DATA),
|
||||
|
||||
.ADDRD(B1ADDR),
|
||||
.DIA(B1DATA),
|
||||
.DIB(B1DATA),
|
||||
.DIC(B1DATA),
|
||||
.DID(B1DATA),
|
||||
.WCLK(CLK1),
|
||||
.WE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__XILINX_RAM64X1Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
|
||||
parameter [63:0] INIT = 64'bx;
|
||||
parameter CLKPOL2 = 1;
|
||||
input CLK1;
|
||||
|
||||
input [5:0] A1ADDR, A2ADDR, A3ADDR;
|
||||
output A1DATA, A2DATA, A3DATA;
|
||||
|
||||
input [5:0] B1ADDR;
|
||||
input B1DATA;
|
||||
input B1EN;
|
||||
|
||||
RAM64M #(
|
||||
.INIT_A(INIT),
|
||||
.INIT_B(INIT),
|
||||
.INIT_C(INIT),
|
||||
.INIT_D(INIT),
|
||||
.IS_WCLK_INVERTED(!CLKPOL2)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ADDRA(A1ADDR),
|
||||
.ADDRB(A2ADDR),
|
||||
.ADDRC(A3ADDR),
|
||||
.DOA(A1DATA),
|
||||
.DOB(A2DATA),
|
||||
.DOC(A3DATA),
|
||||
|
||||
.ADDRD(B1ADDR),
|
||||
.DIA(B1DATA),
|
||||
.DIB(B1DATA),
|
||||
.DIC(B1DATA),
|
||||
.DID(B1DATA),
|
||||
.WCLK(CLK1),
|
||||
.WE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7.
|
||||
# The corresponding mapping file is lutrams_xc5v_map.v
|
||||
|
||||
# Single-port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_SP_ {
|
||||
cost 8;
|
||||
widthscale;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 8 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 4 global;
|
||||
}
|
||||
option "ABITS" 7 {
|
||||
abits 7;
|
||||
widths 2 global;
|
||||
}
|
||||
option "ABITS" 8 {
|
||||
abits 8;
|
||||
widths 1 global;
|
||||
}
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
}
|
||||
|
||||
# Dual-port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_DP_ {
|
||||
cost 8;
|
||||
widthscale;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 4 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 2 global;
|
||||
}
|
||||
option "ABITS" 7 {
|
||||
abits 7;
|
||||
widths 1 global;
|
||||
}
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
||||
# Quad-port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_QP_ {
|
||||
cost 7;
|
||||
widthscale;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 2 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 1 global;
|
||||
}
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R0" "R1" "R2" {
|
||||
}
|
||||
}
|
||||
|
||||
# Simple dual port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_SDP_ {
|
||||
cost 8;
|
||||
widthscale 7;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 6 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 3 global;
|
||||
}
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port sw "W" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,901 @@
|
|||
// LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7, Ultrascale.
|
||||
// The definitions are in lutrams_xc5v.txt (everything but Ultrascale)
|
||||
// and lutrams_xcu.txt (Ultrascale).
|
||||
|
||||
|
||||
module $__XILINX_LUTRAM_SP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_ABITS = 5;
|
||||
parameter WIDTH = 8;
|
||||
parameter BITS_USED = 0;
|
||||
|
||||
output [WIDTH-1:0] PORT_RW_RD_DATA;
|
||||
input [WIDTH-1:0] PORT_RW_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
|
||||
input PORT_RW_WR_EN;
|
||||
input PORT_RW_CLK;
|
||||
|
||||
function [(1 << OPTION_ABITS)-1:0] init_slice;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
|
||||
init_slice[i] = INIT[i * WIDTH + idx];
|
||||
endfunction
|
||||
|
||||
function [(2 << OPTION_ABITS)-1:0] init_slice2;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
|
||||
init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
|
||||
endfunction
|
||||
|
||||
generate
|
||||
case(OPTION_ABITS)
|
||||
5: if (WIDTH == 8)
|
||||
RAM32M
|
||||
#(
|
||||
.INIT_D(init_slice2(0)),
|
||||
.INIT_C(init_slice2(1)),
|
||||
.INIT_B(init_slice2(2)),
|
||||
.INIT_A(init_slice2(3)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_RW_RD_DATA[7:6]),
|
||||
.DOB(PORT_RW_RD_DATA[5:4]),
|
||||
.DOC(PORT_RW_RD_DATA[3:2]),
|
||||
.DOD(PORT_RW_RD_DATA[1:0]),
|
||||
.DIA(PORT_RW_WR_DATA[7:6]),
|
||||
.DIB(PORT_RW_WR_DATA[5:4]),
|
||||
.DIC(PORT_RW_WR_DATA[3:2]),
|
||||
.DID(PORT_RW_WR_DATA[1:0]),
|
||||
.ADDRA(PORT_RW_ADDR),
|
||||
.ADDRB(PORT_RW_ADDR),
|
||||
.ADDRC(PORT_RW_ADDR),
|
||||
.ADDRD(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
else
|
||||
RAM32M16
|
||||
#(
|
||||
.INIT_H(init_slice2(0)),
|
||||
.INIT_G(init_slice2(1)),
|
||||
.INIT_F(init_slice2(2)),
|
||||
.INIT_E(init_slice2(3)),
|
||||
.INIT_D(init_slice2(4)),
|
||||
.INIT_C(init_slice2(5)),
|
||||
.INIT_B(init_slice2(6)),
|
||||
.INIT_A(init_slice2(7)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_RW_RD_DATA[15:14]),
|
||||
.DOB(PORT_RW_RD_DATA[13:12]),
|
||||
.DOC(PORT_RW_RD_DATA[11:10]),
|
||||
.DOD(PORT_RW_RD_DATA[9:8]),
|
||||
.DOE(PORT_RW_RD_DATA[7:6]),
|
||||
.DOF(PORT_RW_RD_DATA[5:4]),
|
||||
.DOG(PORT_RW_RD_DATA[3:2]),
|
||||
.DOH(PORT_RW_RD_DATA[1:0]),
|
||||
.DIA(PORT_RW_WR_DATA[15:14]),
|
||||
.DIB(PORT_RW_WR_DATA[13:12]),
|
||||
.DIC(PORT_RW_WR_DATA[11:10]),
|
||||
.DID(PORT_RW_WR_DATA[9:8]),
|
||||
.DIE(PORT_RW_WR_DATA[7:6]),
|
||||
.DIF(PORT_RW_WR_DATA[5:4]),
|
||||
.DIG(PORT_RW_WR_DATA[3:2]),
|
||||
.DIH(PORT_RW_WR_DATA[1:0]),
|
||||
.ADDRA(PORT_RW_ADDR),
|
||||
.ADDRB(PORT_RW_ADDR),
|
||||
.ADDRC(PORT_RW_ADDR),
|
||||
.ADDRD(PORT_RW_ADDR),
|
||||
.ADDRE(PORT_RW_ADDR),
|
||||
.ADDRF(PORT_RW_ADDR),
|
||||
.ADDRG(PORT_RW_ADDR),
|
||||
.ADDRH(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
6: begin
|
||||
genvar i;
|
||||
for (i = 0; i < WIDTH; i = i + 1)
|
||||
if (BITS_USED[i])
|
||||
RAM64X1S
|
||||
#(
|
||||
.INIT(init_slice(i)),
|
||||
)
|
||||
slice
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.A4(PORT_RW_ADDR[4]),
|
||||
.A5(PORT_RW_ADDR[5]),
|
||||
.D(PORT_RW_WR_DATA[i]),
|
||||
.O(PORT_RW_RD_DATA[i]),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
end
|
||||
7: begin
|
||||
genvar i;
|
||||
for (i = 0; i < WIDTH; i = i + 1)
|
||||
if (BITS_USED[i])
|
||||
RAM128X1S
|
||||
#(
|
||||
.INIT(init_slice(i)),
|
||||
)
|
||||
slice
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.A4(PORT_RW_ADDR[4]),
|
||||
.A5(PORT_RW_ADDR[5]),
|
||||
.A6(PORT_RW_ADDR[6]),
|
||||
.D(PORT_RW_WR_DATA[i]),
|
||||
.O(PORT_RW_RD_DATA[i]),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
end
|
||||
8: begin
|
||||
genvar i;
|
||||
for (i = 0; i < WIDTH; i = i + 1)
|
||||
if (BITS_USED[i])
|
||||
RAM256X1S
|
||||
#(
|
||||
.INIT(init_slice(i)),
|
||||
)
|
||||
slice
|
||||
(
|
||||
.A(PORT_RW_ADDR),
|
||||
.D(PORT_RW_WR_DATA[i]),
|
||||
.O(PORT_RW_RD_DATA[i]),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
end
|
||||
9: begin
|
||||
genvar i;
|
||||
for (i = 0; i < WIDTH; i = i + 1)
|
||||
if (BITS_USED[i])
|
||||
RAM512X1S
|
||||
#(
|
||||
.INIT(init_slice(i)),
|
||||
)
|
||||
slice
|
||||
(
|
||||
.A(PORT_RW_ADDR),
|
||||
.D(PORT_RW_WR_DATA[i]),
|
||||
.O(PORT_RW_RD_DATA[i]),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
end
|
||||
default:
|
||||
$error("invalid OPTION_ABITS/WIDTH combination");
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_LUTRAM_DP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_ABITS = 5;
|
||||
parameter WIDTH = 4;
|
||||
parameter BITS_USED = 0;
|
||||
|
||||
output [WIDTH-1:0] PORT_RW_RD_DATA;
|
||||
input [WIDTH-1:0] PORT_RW_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
|
||||
input PORT_RW_WR_EN;
|
||||
input PORT_RW_CLK;
|
||||
|
||||
output [WIDTH-1:0] PORT_R_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R_ADDR;
|
||||
|
||||
function [(1 << OPTION_ABITS)-1:0] init_slice;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
|
||||
init_slice[i] = INIT[i * WIDTH + idx];
|
||||
endfunction
|
||||
|
||||
function [(2 << OPTION_ABITS)-1:0] init_slice2;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
|
||||
init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
|
||||
endfunction
|
||||
|
||||
generate
|
||||
case (OPTION_ABITS)
|
||||
5: if (WIDTH == 4)
|
||||
RAM32M
|
||||
#(
|
||||
.INIT_D(init_slice2(0)),
|
||||
.INIT_C(init_slice2(0)),
|
||||
.INIT_B(init_slice2(1)),
|
||||
.INIT_A(init_slice2(1)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R_RD_DATA[3:2]),
|
||||
.DOB(PORT_RW_RD_DATA[3:2]),
|
||||
.DOC(PORT_R_RD_DATA[1:0]),
|
||||
.DOD(PORT_RW_RD_DATA[1:0]),
|
||||
.DIA(PORT_RW_WR_DATA[3:2]),
|
||||
.DIB(PORT_RW_WR_DATA[3:2]),
|
||||
.DIC(PORT_RW_WR_DATA[1:0]),
|
||||
.DID(PORT_RW_WR_DATA[1:0]),
|
||||
.ADDRA(PORT_R_ADDR),
|
||||
.ADDRB(PORT_RW_ADDR),
|
||||
.ADDRC(PORT_R_ADDR),
|
||||
.ADDRD(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
else
|
||||
RAM32M16
|
||||
#(
|
||||
.INIT_H(init_slice2(0)),
|
||||
.INIT_G(init_slice2(0)),
|
||||
.INIT_F(init_slice2(1)),
|
||||
.INIT_E(init_slice2(1)),
|
||||
.INIT_D(init_slice2(2)),
|
||||
.INIT_C(init_slice2(2)),
|
||||
.INIT_B(init_slice2(3)),
|
||||
.INIT_A(init_slice2(3)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R_RD_DATA[7:6]),
|
||||
.DOB(PORT_RW_RD_DATA[7:6]),
|
||||
.DOC(PORT_R_RD_DATA[5:4]),
|
||||
.DOD(PORT_RW_RD_DATA[5:4]),
|
||||
.DOE(PORT_R_RD_DATA[3:2]),
|
||||
.DOF(PORT_RW_RD_DATA[3:2]),
|
||||
.DOG(PORT_R_RD_DATA[1:0]),
|
||||
.DOH(PORT_RW_RD_DATA[1:0]),
|
||||
.DIA(PORT_RW_WR_DATA[7:6]),
|
||||
.DIB(PORT_RW_WR_DATA[7:6]),
|
||||
.DIC(PORT_RW_WR_DATA[5:4]),
|
||||
.DID(PORT_RW_WR_DATA[5:4]),
|
||||
.DIE(PORT_RW_WR_DATA[3:2]),
|
||||
.DIF(PORT_RW_WR_DATA[3:2]),
|
||||
.DIG(PORT_RW_WR_DATA[1:0]),
|
||||
.DIH(PORT_RW_WR_DATA[1:0]),
|
||||
.ADDRA(PORT_R_ADDR),
|
||||
.ADDRB(PORT_RW_ADDR),
|
||||
.ADDRC(PORT_R_ADDR),
|
||||
.ADDRD(PORT_RW_ADDR),
|
||||
.ADDRE(PORT_R_ADDR),
|
||||
.ADDRF(PORT_RW_ADDR),
|
||||
.ADDRG(PORT_R_ADDR),
|
||||
.ADDRH(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
6: begin
|
||||
genvar i;
|
||||
for (i = 0; i < WIDTH; i = i + 1)
|
||||
if (BITS_USED[i])
|
||||
RAM64X1D
|
||||
#(
|
||||
.INIT(init_slice(i)),
|
||||
)
|
||||
slice
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.A4(PORT_RW_ADDR[4]),
|
||||
.A5(PORT_RW_ADDR[5]),
|
||||
.D(PORT_RW_WR_DATA[i]),
|
||||
.SPO(PORT_RW_RD_DATA[i]),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
.DPRA0(PORT_R_ADDR[0]),
|
||||
.DPRA1(PORT_R_ADDR[1]),
|
||||
.DPRA2(PORT_R_ADDR[2]),
|
||||
.DPRA3(PORT_R_ADDR[3]),
|
||||
.DPRA4(PORT_R_ADDR[4]),
|
||||
.DPRA5(PORT_R_ADDR[5]),
|
||||
.DPO(PORT_R_RD_DATA[i]),
|
||||
);
|
||||
end
|
||||
7: begin
|
||||
genvar i;
|
||||
for (i = 0; i < WIDTH; i = i + 1)
|
||||
if (BITS_USED[i])
|
||||
RAM128X1D
|
||||
#(
|
||||
.INIT(init_slice(i)),
|
||||
)
|
||||
slice
|
||||
(
|
||||
.A(PORT_RW_ADDR),
|
||||
.D(PORT_RW_WR_DATA[i]),
|
||||
.SPO(PORT_RW_RD_DATA[i]),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
.DPRA(PORT_R_ADDR),
|
||||
.DPO(PORT_R_RD_DATA[i]),
|
||||
);
|
||||
end
|
||||
8: begin
|
||||
genvar i;
|
||||
for (i = 0; i < WIDTH; i = i + 1)
|
||||
if (BITS_USED[i])
|
||||
RAM256X1D
|
||||
#(
|
||||
.INIT(init_slice(i)),
|
||||
)
|
||||
slice
|
||||
(
|
||||
.A(PORT_RW_ADDR),
|
||||
.D(PORT_RW_WR_DATA[i]),
|
||||
.SPO(PORT_RW_RD_DATA[i]),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
.DPRA(PORT_R_ADDR),
|
||||
.DPO(PORT_R_RD_DATA[i]),
|
||||
);
|
||||
end
|
||||
default:
|
||||
$error("invalid OPTION_ABITS/WIDTH combination");
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_LUTRAM_QP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_ABITS = 5;
|
||||
parameter WIDTH = 2;
|
||||
parameter BITS_USED = 0;
|
||||
|
||||
output [WIDTH-1:0] PORT_RW_RD_DATA;
|
||||
input [WIDTH-1:0] PORT_RW_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
|
||||
input PORT_RW_WR_EN;
|
||||
input PORT_RW_CLK;
|
||||
|
||||
output [WIDTH-1:0] PORT_R0_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R0_ADDR;
|
||||
output [WIDTH-1:0] PORT_R1_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R1_ADDR;
|
||||
output [WIDTH-1:0] PORT_R2_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R2_ADDR;
|
||||
|
||||
function [(1 << OPTION_ABITS)-1:0] init_slice;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
|
||||
init_slice[i] = INIT[i * WIDTH + idx];
|
||||
endfunction
|
||||
|
||||
function [(2 << OPTION_ABITS)-1:0] init_slice2;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
|
||||
init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
|
||||
endfunction
|
||||
|
||||
generate
|
||||
case (OPTION_ABITS)
|
||||
5: if (WIDTH == 2)
|
||||
RAM32M
|
||||
#(
|
||||
.INIT_D(init_slice2(0)),
|
||||
.INIT_C(init_slice2(0)),
|
||||
.INIT_B(init_slice2(0)),
|
||||
.INIT_A(init_slice2(0)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R2_RD_DATA[1:0]),
|
||||
.DOB(PORT_R1_RD_DATA[1:0]),
|
||||
.DOC(PORT_R0_RD_DATA[1:0]),
|
||||
.DOD(PORT_RW_RD_DATA[1:0]),
|
||||
.DIA(PORT_RW_WR_DATA[1:0]),
|
||||
.DIB(PORT_RW_WR_DATA[1:0]),
|
||||
.DIC(PORT_RW_WR_DATA[1:0]),
|
||||
.DID(PORT_RW_WR_DATA[1:0]),
|
||||
.ADDRA(PORT_R2_ADDR),
|
||||
.ADDRB(PORT_R1_ADDR),
|
||||
.ADDRC(PORT_R0_ADDR),
|
||||
.ADDRD(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
else
|
||||
RAM32M16
|
||||
#(
|
||||
.INIT_H(init_slice2(0)),
|
||||
.INIT_G(init_slice2(0)),
|
||||
.INIT_F(init_slice2(0)),
|
||||
.INIT_E(init_slice2(0)),
|
||||
.INIT_D(init_slice2(1)),
|
||||
.INIT_C(init_slice2(1)),
|
||||
.INIT_B(init_slice2(1)),
|
||||
.INIT_A(init_slice2(1)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R2_RD_DATA[3:2]),
|
||||
.DOB(PORT_R1_RD_DATA[3:2]),
|
||||
.DOC(PORT_R0_RD_DATA[3:2]),
|
||||
.DOD(PORT_RW_RD_DATA[3:2]),
|
||||
.DOE(PORT_R2_RD_DATA[1:0]),
|
||||
.DOF(PORT_R1_RD_DATA[1:0]),
|
||||
.DOG(PORT_R0_RD_DATA[1:0]),
|
||||
.DOH(PORT_RW_RD_DATA[1:0]),
|
||||
.DIA(PORT_RW_WR_DATA[3:2]),
|
||||
.DIB(PORT_RW_WR_DATA[3:2]),
|
||||
.DIC(PORT_RW_WR_DATA[3:2]),
|
||||
.DID(PORT_RW_WR_DATA[3:2]),
|
||||
.DIE(PORT_RW_WR_DATA[1:0]),
|
||||
.DIF(PORT_RW_WR_DATA[1:0]),
|
||||
.DIG(PORT_RW_WR_DATA[1:0]),
|
||||
.DIH(PORT_RW_WR_DATA[1:0]),
|
||||
.ADDRA(PORT_R2_ADDR),
|
||||
.ADDRB(PORT_R1_ADDR),
|
||||
.ADDRC(PORT_R0_ADDR),
|
||||
.ADDRD(PORT_RW_ADDR),
|
||||
.ADDRE(PORT_R2_ADDR),
|
||||
.ADDRF(PORT_R1_ADDR),
|
||||
.ADDRG(PORT_R0_ADDR),
|
||||
.ADDRH(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
6: if (WIDTH == 1)
|
||||
RAM64M
|
||||
#(
|
||||
.INIT_D(init_slice(0)),
|
||||
.INIT_C(init_slice(0)),
|
||||
.INIT_B(init_slice(0)),
|
||||
.INIT_A(init_slice(0)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R2_RD_DATA[0]),
|
||||
.DOB(PORT_R1_RD_DATA[0]),
|
||||
.DOC(PORT_R0_RD_DATA[0]),
|
||||
.DOD(PORT_RW_RD_DATA[0]),
|
||||
.DIA(PORT_RW_WR_DATA[0]),
|
||||
.DIB(PORT_RW_WR_DATA[0]),
|
||||
.DIC(PORT_RW_WR_DATA[0]),
|
||||
.DID(PORT_RW_WR_DATA[0]),
|
||||
.ADDRA(PORT_R2_ADDR),
|
||||
.ADDRB(PORT_R1_ADDR),
|
||||
.ADDRC(PORT_R0_ADDR),
|
||||
.ADDRD(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
else
|
||||
RAM64M8
|
||||
#(
|
||||
.INIT_H(init_slice(0)),
|
||||
.INIT_G(init_slice(0)),
|
||||
.INIT_F(init_slice(0)),
|
||||
.INIT_E(init_slice(0)),
|
||||
.INIT_D(init_slice(1)),
|
||||
.INIT_C(init_slice(1)),
|
||||
.INIT_B(init_slice(1)),
|
||||
.INIT_A(init_slice(1)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R2_RD_DATA[1]),
|
||||
.DOB(PORT_R1_RD_DATA[1]),
|
||||
.DOC(PORT_R0_RD_DATA[1]),
|
||||
.DOD(PORT_RW_RD_DATA[1]),
|
||||
.DOE(PORT_R2_RD_DATA[0]),
|
||||
.DOF(PORT_R1_RD_DATA[0]),
|
||||
.DOG(PORT_R0_RD_DATA[0]),
|
||||
.DOH(PORT_RW_RD_DATA[0]),
|
||||
.DIA(PORT_RW_WR_DATA[1]),
|
||||
.DIB(PORT_RW_WR_DATA[1]),
|
||||
.DIC(PORT_RW_WR_DATA[1]),
|
||||
.DID(PORT_RW_WR_DATA[1]),
|
||||
.DIE(PORT_RW_WR_DATA[0]),
|
||||
.DIF(PORT_RW_WR_DATA[0]),
|
||||
.DIG(PORT_RW_WR_DATA[0]),
|
||||
.DIH(PORT_RW_WR_DATA[0]),
|
||||
.ADDRA(PORT_R2_ADDR),
|
||||
.ADDRB(PORT_R1_ADDR),
|
||||
.ADDRC(PORT_R0_ADDR),
|
||||
.ADDRD(PORT_RW_ADDR),
|
||||
.ADDRE(PORT_R2_ADDR),
|
||||
.ADDRF(PORT_R1_ADDR),
|
||||
.ADDRG(PORT_R0_ADDR),
|
||||
.ADDRH(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
default:
|
||||
$error("invalid OPTION_ABITS/WIDTH combination");
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_LUTRAM_OP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_ABITS = 5;
|
||||
parameter WIDTH = 2;
|
||||
parameter BITS_USED = 0;
|
||||
|
||||
output [WIDTH-1:0] PORT_RW_RD_DATA;
|
||||
input [WIDTH-1:0] PORT_RW_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
|
||||
input PORT_RW_WR_EN;
|
||||
input PORT_RW_CLK;
|
||||
|
||||
output [WIDTH-1:0] PORT_R0_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R0_ADDR;
|
||||
output [WIDTH-1:0] PORT_R1_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R1_ADDR;
|
||||
output [WIDTH-1:0] PORT_R2_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R2_ADDR;
|
||||
output [WIDTH-1:0] PORT_R3_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R3_ADDR;
|
||||
output [WIDTH-1:0] PORT_R4_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R4_ADDR;
|
||||
output [WIDTH-1:0] PORT_R5_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R5_ADDR;
|
||||
output [WIDTH-1:0] PORT_R6_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R6_ADDR;
|
||||
|
||||
generate
|
||||
case (OPTION_ABITS)
|
||||
5: RAM32M16
|
||||
#(
|
||||
.INIT_H(INIT),
|
||||
.INIT_G(INIT),
|
||||
.INIT_F(INIT),
|
||||
.INIT_E(INIT),
|
||||
.INIT_D(INIT),
|
||||
.INIT_C(INIT),
|
||||
.INIT_B(INIT),
|
||||
.INIT_A(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R6_RD_DATA),
|
||||
.DOB(PORT_R5_RD_DATA),
|
||||
.DOC(PORT_R4_RD_DATA),
|
||||
.DOD(PORT_R3_RD_DATA),
|
||||
.DOE(PORT_R2_RD_DATA),
|
||||
.DOF(PORT_R1_RD_DATA),
|
||||
.DOG(PORT_R0_RD_DATA),
|
||||
.DOH(PORT_RW_RD_DATA),
|
||||
.DIA(PORT_RW_WR_DATA),
|
||||
.DIB(PORT_RW_WR_DATA),
|
||||
.DIC(PORT_RW_WR_DATA),
|
||||
.DID(PORT_RW_WR_DATA),
|
||||
.DIE(PORT_RW_WR_DATA),
|
||||
.DIF(PORT_RW_WR_DATA),
|
||||
.DIG(PORT_RW_WR_DATA),
|
||||
.DIH(PORT_RW_WR_DATA),
|
||||
.ADDRA(PORT_R6_ADDR),
|
||||
.ADDRB(PORT_R5_ADDR),
|
||||
.ADDRC(PORT_R4_ADDR),
|
||||
.ADDRD(PORT_R3_ADDR),
|
||||
.ADDRE(PORT_R2_ADDR),
|
||||
.ADDRF(PORT_R1_ADDR),
|
||||
.ADDRG(PORT_R0_ADDR),
|
||||
.ADDRH(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
6: RAM64M8
|
||||
#(
|
||||
.INIT_H(INIT),
|
||||
.INIT_G(INIT),
|
||||
.INIT_F(INIT),
|
||||
.INIT_E(INIT),
|
||||
.INIT_D(INIT),
|
||||
.INIT_C(INIT),
|
||||
.INIT_B(INIT),
|
||||
.INIT_A(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R6_RD_DATA),
|
||||
.DOB(PORT_R5_RD_DATA),
|
||||
.DOC(PORT_R4_RD_DATA),
|
||||
.DOD(PORT_R3_RD_DATA),
|
||||
.DOE(PORT_R2_RD_DATA),
|
||||
.DOF(PORT_R1_RD_DATA),
|
||||
.DOG(PORT_R0_RD_DATA),
|
||||
.DOH(PORT_RW_RD_DATA),
|
||||
.DIA(PORT_RW_WR_DATA),
|
||||
.DIB(PORT_RW_WR_DATA),
|
||||
.DIC(PORT_RW_WR_DATA),
|
||||
.DID(PORT_RW_WR_DATA),
|
||||
.DIE(PORT_RW_WR_DATA),
|
||||
.DIF(PORT_RW_WR_DATA),
|
||||
.DIG(PORT_RW_WR_DATA),
|
||||
.DIH(PORT_RW_WR_DATA),
|
||||
.ADDRA(PORT_R6_ADDR),
|
||||
.ADDRB(PORT_R5_ADDR),
|
||||
.ADDRC(PORT_R4_ADDR),
|
||||
.ADDRD(PORT_R3_ADDR),
|
||||
.ADDRE(PORT_R2_ADDR),
|
||||
.ADDRF(PORT_R1_ADDR),
|
||||
.ADDRG(PORT_R0_ADDR),
|
||||
.ADDRH(PORT_RW_ADDR),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
default:
|
||||
$error("invalid OPTION_ABITS/WIDTH combination");
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_LUTRAM_SDP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_ABITS = 5;
|
||||
parameter WIDTH = 6;
|
||||
parameter BITS_USED = 0;
|
||||
|
||||
input [WIDTH-1:0] PORT_W_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_W_ADDR;
|
||||
input PORT_W_WR_EN;
|
||||
input PORT_W_CLK;
|
||||
|
||||
output [WIDTH-1:0] PORT_R_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R_ADDR;
|
||||
|
||||
function [(1 << OPTION_ABITS)-1:0] init_slice;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
|
||||
init_slice[i] = INIT[i * WIDTH + idx];
|
||||
endfunction
|
||||
|
||||
function [(2 << OPTION_ABITS)-1:0] init_slice2;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
|
||||
init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
|
||||
endfunction
|
||||
|
||||
generate
|
||||
case (OPTION_ABITS)
|
||||
5: if (WIDTH == 6)
|
||||
RAM32M
|
||||
#(
|
||||
.INIT_C(init_slice2(0)),
|
||||
.INIT_B(init_slice2(1)),
|
||||
.INIT_A(init_slice2(2)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R_RD_DATA[5:4]),
|
||||
.DOB(PORT_R_RD_DATA[3:2]),
|
||||
.DOC(PORT_R_RD_DATA[1:0]),
|
||||
.DIA(PORT_W_WR_DATA[5:4]),
|
||||
.DIB(PORT_W_WR_DATA[3:2]),
|
||||
.DIC(PORT_W_WR_DATA[1:0]),
|
||||
.ADDRA(PORT_R_ADDR),
|
||||
.ADDRB(PORT_R_ADDR),
|
||||
.ADDRC(PORT_R_ADDR),
|
||||
.ADDRD(PORT_W_ADDR),
|
||||
.WE(PORT_W_WR_EN),
|
||||
.WCLK(PORT_W_CLK),
|
||||
);
|
||||
else
|
||||
RAM32M16
|
||||
#(
|
||||
.INIT_G(init_slice2(0)),
|
||||
.INIT_F(init_slice2(1)),
|
||||
.INIT_E(init_slice2(2)),
|
||||
.INIT_D(init_slice2(3)),
|
||||
.INIT_C(init_slice2(4)),
|
||||
.INIT_B(init_slice2(5)),
|
||||
.INIT_A(init_slice2(6)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R_RD_DATA[13:12]),
|
||||
.DOB(PORT_R_RD_DATA[11:10]),
|
||||
.DOC(PORT_R_RD_DATA[9:8]),
|
||||
.DOD(PORT_R_RD_DATA[7:6]),
|
||||
.DOE(PORT_R_RD_DATA[5:4]),
|
||||
.DOF(PORT_R_RD_DATA[3:2]),
|
||||
.DOG(PORT_R_RD_DATA[1:0]),
|
||||
.DIA(PORT_W_WR_DATA[13:12]),
|
||||
.DIB(PORT_W_WR_DATA[11:10]),
|
||||
.DIC(PORT_W_WR_DATA[9:8]),
|
||||
.DID(PORT_W_WR_DATA[7:6]),
|
||||
.DIE(PORT_W_WR_DATA[5:4]),
|
||||
.DIF(PORT_W_WR_DATA[3:2]),
|
||||
.DIG(PORT_W_WR_DATA[1:0]),
|
||||
.ADDRA(PORT_R_ADDR),
|
||||
.ADDRB(PORT_R_ADDR),
|
||||
.ADDRC(PORT_R_ADDR),
|
||||
.ADDRD(PORT_R_ADDR),
|
||||
.ADDRE(PORT_R_ADDR),
|
||||
.ADDRF(PORT_R_ADDR),
|
||||
.ADDRG(PORT_R_ADDR),
|
||||
.ADDRH(PORT_W_ADDR),
|
||||
.WE(PORT_W_WR_EN),
|
||||
.WCLK(PORT_W_CLK),
|
||||
);
|
||||
6: if (WIDTH == 3)
|
||||
RAM64M
|
||||
#(
|
||||
.INIT_C(init_slice(0)),
|
||||
.INIT_B(init_slice(1)),
|
||||
.INIT_A(init_slice(2)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R_RD_DATA[2]),
|
||||
.DOB(PORT_R_RD_DATA[1]),
|
||||
.DOC(PORT_R_RD_DATA[0]),
|
||||
.DIA(PORT_W_WR_DATA[2]),
|
||||
.DIB(PORT_W_WR_DATA[1]),
|
||||
.DIC(PORT_W_WR_DATA[0]),
|
||||
.ADDRA(PORT_R_ADDR),
|
||||
.ADDRB(PORT_R_ADDR),
|
||||
.ADDRC(PORT_R_ADDR),
|
||||
.ADDRD(PORT_W_ADDR),
|
||||
.WE(PORT_W_WR_EN),
|
||||
.WCLK(PORT_W_CLK),
|
||||
);
|
||||
else
|
||||
RAM64M8
|
||||
#(
|
||||
.INIT_G(init_slice(0)),
|
||||
.INIT_F(init_slice(1)),
|
||||
.INIT_E(init_slice(2)),
|
||||
.INIT_D(init_slice(3)),
|
||||
.INIT_C(init_slice(4)),
|
||||
.INIT_B(init_slice(5)),
|
||||
.INIT_A(init_slice(6)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R_RD_DATA[6]),
|
||||
.DOB(PORT_R_RD_DATA[5]),
|
||||
.DOC(PORT_R_RD_DATA[4]),
|
||||
.DOD(PORT_R_RD_DATA[3]),
|
||||
.DOE(PORT_R_RD_DATA[2]),
|
||||
.DOF(PORT_R_RD_DATA[1]),
|
||||
.DOG(PORT_R_RD_DATA[0]),
|
||||
.DIA(PORT_W_WR_DATA[6]),
|
||||
.DIB(PORT_W_WR_DATA[5]),
|
||||
.DIC(PORT_W_WR_DATA[4]),
|
||||
.DID(PORT_W_WR_DATA[3]),
|
||||
.DIE(PORT_W_WR_DATA[2]),
|
||||
.DIF(PORT_W_WR_DATA[1]),
|
||||
.DIG(PORT_W_WR_DATA[0]),
|
||||
.ADDRA(PORT_R_ADDR),
|
||||
.ADDRB(PORT_R_ADDR),
|
||||
.ADDRC(PORT_R_ADDR),
|
||||
.ADDRD(PORT_R_ADDR),
|
||||
.ADDRE(PORT_R_ADDR),
|
||||
.ADDRF(PORT_R_ADDR),
|
||||
.ADDRG(PORT_R_ADDR),
|
||||
.ADDRH(PORT_W_ADDR),
|
||||
.WE(PORT_W_WR_EN),
|
||||
.WCLK(PORT_W_CLK),
|
||||
);
|
||||
default:
|
||||
$error("invalid OPTION_ABITS/WIDTH combination");
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_LUTRAM_64X8SW_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_ABITS = 9;
|
||||
parameter PORT_RW_WR_WIDTH = 1;
|
||||
parameter PORT_RW_RD_WIDTH = 8;
|
||||
|
||||
output [PORT_RW_RD_WIDTH-1:0] PORT_RW_RD_DATA;
|
||||
input [PORT_RW_WR_WIDTH-1:0] PORT_RW_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
|
||||
input PORT_RW_WR_EN;
|
||||
input PORT_RW_CLK;
|
||||
|
||||
function [63:0] init_slice;
|
||||
input integer idx;
|
||||
integer i;
|
||||
for (i = 0; i < 64; i = i + 1)
|
||||
init_slice[i] = INIT[i * 8 + idx];
|
||||
endfunction
|
||||
|
||||
RAM64X8SW
|
||||
#(
|
||||
.INIT_A(init_slice(7)),
|
||||
.INIT_B(init_slice(6)),
|
||||
.INIT_C(init_slice(5)),
|
||||
.INIT_D(init_slice(4)),
|
||||
.INIT_E(init_slice(3)),
|
||||
.INIT_F(init_slice(2)),
|
||||
.INIT_G(init_slice(1)),
|
||||
.INIT_H(init_slice(0)),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.A(PORT_RW_ADDR[8:3]),
|
||||
.WSEL(PORT_RW_ADDR[2:0]),
|
||||
.D(PORT_RW_WR_DATA),
|
||||
.O(PORT_RW_RD_DATA),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module $__XILINX_LUTRAM_32X16DR8_ (...);
|
||||
|
||||
parameter OPTION_ABITS = 6;
|
||||
parameter BITS_USED = 0;
|
||||
parameter PORT_W_WIDTH = 14;
|
||||
parameter PORT_R_WIDTH = 7;
|
||||
|
||||
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_W_ADDR;
|
||||
input PORT_W_WR_EN;
|
||||
input PORT_W_CLK;
|
||||
|
||||
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R_ADDR;
|
||||
|
||||
RAM32X16DR8 _TECHMAP_REPLACE_
|
||||
(
|
||||
.DOA(PORT_R_RD_DATA[6]),
|
||||
.DOB(PORT_R_RD_DATA[5]),
|
||||
.DOC(PORT_R_RD_DATA[4]),
|
||||
.DOD(PORT_R_RD_DATA[3]),
|
||||
.DOE(PORT_R_RD_DATA[2]),
|
||||
.DOF(PORT_R_RD_DATA[1]),
|
||||
.DOG(PORT_R_RD_DATA[0]),
|
||||
.DIA({PORT_W_WR_DATA[13], PORT_W_WR_DATA[6]}),
|
||||
.DIB({PORT_W_WR_DATA[12], PORT_W_WR_DATA[5]}),
|
||||
.DIC({PORT_W_WR_DATA[11], PORT_W_WR_DATA[4]}),
|
||||
.DID({PORT_W_WR_DATA[10], PORT_W_WR_DATA[3]}),
|
||||
.DIE({PORT_W_WR_DATA[9], PORT_W_WR_DATA[2]}),
|
||||
.DIF({PORT_W_WR_DATA[8], PORT_W_WR_DATA[1]}),
|
||||
.DIG({PORT_W_WR_DATA[7], PORT_W_WR_DATA[0]}),
|
||||
.ADDRA(PORT_R_ADDR),
|
||||
.ADDRB(PORT_R_ADDR),
|
||||
.ADDRC(PORT_R_ADDR),
|
||||
.ADDRD(PORT_R_ADDR),
|
||||
.ADDRE(PORT_R_ADDR),
|
||||
.ADDRF(PORT_R_ADDR),
|
||||
.ADDRG(PORT_R_ADDR),
|
||||
.ADDRH(PORT_W_ADDR[5:1]),
|
||||
.WE(PORT_W_WR_EN),
|
||||
.WCLK(PORT_W_CLK),
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
# LUT RAMs for Ultrascale.
|
||||
# The corresponding mapping file is lutrams_xc5v_map.v
|
||||
|
||||
# Single-port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_SP_ {
|
||||
cost 16;
|
||||
widthscale;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 16 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 8 global;
|
||||
}
|
||||
option "ABITS" 7 {
|
||||
abits 7;
|
||||
widths 4 global;
|
||||
}
|
||||
option "ABITS" 8 {
|
||||
abits 8;
|
||||
widths 2 global;
|
||||
}
|
||||
option "ABITS" 16 {
|
||||
abits 16;
|
||||
widths 1 global;
|
||||
}
|
||||
init any;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
}
|
||||
|
||||
# Dual-port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_DP_ {
|
||||
cost 16;
|
||||
widthscale;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 8 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 4 global;
|
||||
}
|
||||
option "ABITS" 7 {
|
||||
abits 7;
|
||||
widths 2 global;
|
||||
}
|
||||
option "ABITS" 8 {
|
||||
abits 8;
|
||||
widths 1 global;
|
||||
}
|
||||
init any;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
||||
# Quad-port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_QP_ {
|
||||
cost 16;
|
||||
widthscale;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 4 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 2 global;
|
||||
}
|
||||
init any;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R0" "R1" "R2" {
|
||||
}
|
||||
}
|
||||
|
||||
# Octal-port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_OP_ {
|
||||
cost 16;
|
||||
widthscale;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 2 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 1 global;
|
||||
}
|
||||
init any;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R0" "R1" "R2" "R3" "R4" "R5" "R6" {
|
||||
}
|
||||
}
|
||||
|
||||
# Simple dual port RAMs.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_SDP_ {
|
||||
cost 16;
|
||||
widthscale;
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
widths 14 global;
|
||||
}
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
widths 7 global;
|
||||
}
|
||||
init any;
|
||||
prune_rom;
|
||||
port sw "W" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
||||
# Wide-read RAM.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_64X8SW_ {
|
||||
cost 16;
|
||||
abits 9;
|
||||
widths 1 2 4 8 per_port;
|
||||
init any;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
width rd 8 wr 1;
|
||||
clock posedge;
|
||||
}
|
||||
}
|
||||
|
||||
# Wide-write RAM.
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_32X16DR8_ {
|
||||
cost 16;
|
||||
widthscale;
|
||||
abits 6;
|
||||
widths 7 14 per_port;
|
||||
# Yes, no initialization capability.
|
||||
prune_rom;
|
||||
port sw "W" {
|
||||
width 14;
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R" {
|
||||
width 7;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
# LUT RAMs for Virtex, Virtex 2, Spartan 3, Virtex 4.
|
||||
# The corresponding mapping file is lutrams_xcv_map.v
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_SP_ {
|
||||
width 1;
|
||||
option "ABITS" 4 {
|
||||
abits 4;
|
||||
cost 3;
|
||||
}
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
cost 5;
|
||||
}
|
||||
ifndef IS_VIRTEX {
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
cost 9;
|
||||
}
|
||||
}
|
||||
ifdef IS_VIRTEX2 {
|
||||
# RAM128X1S
|
||||
option "ABITS" 7 {
|
||||
abits 7;
|
||||
cost 17;
|
||||
}
|
||||
}
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
}
|
||||
|
||||
ram distributed $__XILINX_LUTRAM_DP_ {
|
||||
width 1;
|
||||
option "ABITS" 4 {
|
||||
abits 4;
|
||||
cost 5;
|
||||
}
|
||||
ifdef IS_VIRTEX2 {
|
||||
# RAM32X1D
|
||||
option "ABITS" 5 {
|
||||
abits 5;
|
||||
cost 9;
|
||||
}
|
||||
# RAM64X1D
|
||||
option "ABITS" 6 {
|
||||
abits 6;
|
||||
cost 17;
|
||||
}
|
||||
}
|
||||
init no_undef;
|
||||
prune_rom;
|
||||
port arsw "RW" {
|
||||
clock posedge;
|
||||
}
|
||||
port ar "R" {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
// LUT RAMs for Virtex, Virtex 2, Spartan 3, Virtex 4.
|
||||
// The corresponding definition file is lutrams_xcv.txt
|
||||
|
||||
module $__XILINX_LUTRAM_SP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_ABITS = 4;
|
||||
|
||||
output PORT_RW_RD_DATA;
|
||||
input PORT_RW_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
|
||||
input PORT_RW_WR_EN;
|
||||
input PORT_RW_CLK;
|
||||
|
||||
generate
|
||||
case(OPTION_ABITS)
|
||||
4: RAM16X1S
|
||||
#(
|
||||
.INIT(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.D(PORT_RW_WR_DATA),
|
||||
.O(PORT_RW_RD_DATA),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
5: RAM32X1S
|
||||
#(
|
||||
.INIT(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.A4(PORT_RW_ADDR[4]),
|
||||
.D(PORT_RW_WR_DATA),
|
||||
.O(PORT_RW_RD_DATA),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
6: RAM64X1S
|
||||
#(
|
||||
.INIT(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.A4(PORT_RW_ADDR[4]),
|
||||
.A5(PORT_RW_ADDR[5]),
|
||||
.D(PORT_RW_WR_DATA),
|
||||
.O(PORT_RW_RD_DATA),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
7: RAM128X1S
|
||||
#(
|
||||
.INIT(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.A4(PORT_RW_ADDR[4]),
|
||||
.A5(PORT_RW_ADDR[5]),
|
||||
.A6(PORT_RW_ADDR[6]),
|
||||
.D(PORT_RW_WR_DATA),
|
||||
.O(PORT_RW_RD_DATA),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
);
|
||||
default:
|
||||
$error("invalid OPTION_ABITS");
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
module $__XILINX_LUTRAM_DP_ (...);
|
||||
|
||||
parameter INIT = 0;
|
||||
parameter OPTION_ABITS = 4;
|
||||
|
||||
output PORT_RW_RD_DATA;
|
||||
input PORT_RW_WR_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
|
||||
input PORT_RW_WR_EN;
|
||||
input PORT_RW_CLK;
|
||||
|
||||
output PORT_R_RD_DATA;
|
||||
input [OPTION_ABITS-1:0] PORT_R_ADDR;
|
||||
|
||||
generate
|
||||
case (OPTION_ABITS)
|
||||
4: RAM16X1D
|
||||
#(
|
||||
.INIT(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.D(PORT_RW_WR_DATA),
|
||||
.SPO(PORT_RW_RD_DATA),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
.DPRA0(PORT_R_ADDR[0]),
|
||||
.DPRA1(PORT_R_ADDR[1]),
|
||||
.DPRA2(PORT_R_ADDR[2]),
|
||||
.DPRA3(PORT_R_ADDR[3]),
|
||||
.DPO(PORT_R_RD_DATA),
|
||||
);
|
||||
5: RAM32X1D
|
||||
#(
|
||||
.INIT(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.A4(PORT_RW_ADDR[4]),
|
||||
.D(PORT_RW_WR_DATA),
|
||||
.SPO(PORT_RW_RD_DATA),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
.DPRA0(PORT_R_ADDR[0]),
|
||||
.DPRA1(PORT_R_ADDR[1]),
|
||||
.DPRA2(PORT_R_ADDR[2]),
|
||||
.DPRA3(PORT_R_ADDR[3]),
|
||||
.DPRA4(PORT_R_ADDR[4]),
|
||||
.DPO(PORT_R_RD_DATA),
|
||||
);
|
||||
6: RAM64X1D
|
||||
#(
|
||||
.INIT(INIT),
|
||||
)
|
||||
_TECHMAP_REPLACE_
|
||||
(
|
||||
.A0(PORT_RW_ADDR[0]),
|
||||
.A1(PORT_RW_ADDR[1]),
|
||||
.A2(PORT_RW_ADDR[2]),
|
||||
.A3(PORT_RW_ADDR[3]),
|
||||
.A4(PORT_RW_ADDR[4]),
|
||||
.A5(PORT_RW_ADDR[5]),
|
||||
.D(PORT_RW_WR_DATA),
|
||||
.SPO(PORT_RW_RD_DATA),
|
||||
.WE(PORT_RW_WR_EN),
|
||||
.WCLK(PORT_RW_CLK),
|
||||
.DPRA0(PORT_R_ADDR[0]),
|
||||
.DPRA1(PORT_R_ADDR[1]),
|
||||
.DPRA2(PORT_R_ADDR[2]),
|
||||
.DPRA3(PORT_R_ADDR[3]),
|
||||
.DPRA4(PORT_R_ADDR[4]),
|
||||
.DPRA5(PORT_R_ADDR[5]),
|
||||
.DPO(PORT_R_RD_DATA),
|
||||
);
|
||||
default:
|
||||
$error("invalid OPTION_ABITS");
|
||||
endcase
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -450,56 +450,97 @@ struct SynthXilinxPass : public ScriptPass
|
|||
run("opt_clean");
|
||||
}
|
||||
|
||||
if (check_label("map_uram", "(only if '-uram')")) {
|
||||
if (check_label("map_memory")) {
|
||||
std::string params = "";
|
||||
std::string lutrams_map = "+/xilinx/lutrams_<family>_map.v";
|
||||
std::string brams_map = "+/xilinx/brams_<family>_map.v";
|
||||
if (help_mode) {
|
||||
run("memory_bram -rules +/xilinx/{family}_urams.txt");
|
||||
run("techmap -map +/xilinx/{family}_urams_map.v");
|
||||
} else if (uram) {
|
||||
if (family == "xcup") {
|
||||
run("memory_bram -rules +/xilinx/xcup_urams.txt");
|
||||
run("techmap -map +/xilinx/xcup_urams_map.v");
|
||||
} else {
|
||||
log_warning("UltraRAM inference not supported for family %s.\n", family.c_str());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("map_bram", "(skip if '-nobram')")) {
|
||||
if (help_mode) {
|
||||
run("memory_bram -rules +/xilinx/{family}_brams.txt");
|
||||
run("techmap -map +/xilinx/{family}_brams_map.v");
|
||||
} else if (!nobram) {
|
||||
if (family == "xc2v" || family == "xc2vp" || family == "xc3s" || family == "xc3se") {
|
||||
run("memory_bram -rules +/xilinx/xc2v_brams.txt");
|
||||
run("techmap -map +/xilinx/xc2v_brams_map.v");
|
||||
params = " [...]";
|
||||
} else {
|
||||
if (family == "xcv" || family == "xcve") {
|
||||
params += " -lib +/xilinx/lutrams_xcv.txt";
|
||||
params += " -D IS_VIRTEX";
|
||||
lutrams_map = "+/xilinx/lutrams_xcv_map.v";
|
||||
params += " -lib +/xilinx/brams_xcv.txt";
|
||||
brams_map = "+/xilinx/brams_xcv_map.v";
|
||||
} else if (family == "xc2v" || family == "xc2vp") {
|
||||
params += " -lib +/xilinx/lutrams_xcv.txt";
|
||||
params += " -D IS_VIRTEX2";
|
||||
lutrams_map = "+/xilinx/lutrams_xcv_map.v";
|
||||
params += " -lib +/xilinx/brams_xc2v.txt";
|
||||
brams_map = "+/xilinx/brams_xc2v_map.v";
|
||||
} else if (family == "xc3s" || family == "xc3se") {
|
||||
params += " -lib +/xilinx/lutrams_xcv.txt";
|
||||
lutrams_map = "+/xilinx/lutrams_xcv_map.v";
|
||||
params += " -lib +/xilinx/brams_xc2v.txt";
|
||||
brams_map = "+/xilinx/brams_xc2v_map.v";
|
||||
} else if (family == "xc3sa") {
|
||||
// Superset of Virtex 2 primitives — uses common map file.
|
||||
run("memory_bram -rules +/xilinx/xc3sa_brams.txt");
|
||||
run("techmap -map +/xilinx/xc2v_brams_map.v");
|
||||
params += " -lib +/xilinx/lutrams_xcv.txt";
|
||||
lutrams_map = "+/xilinx/lutrams_xcv_map.v";
|
||||
params += " -lib +/xilinx/brams_xc2v.txt";
|
||||
params += " -D HAS_BE";
|
||||
brams_map = "+/xilinx/brams_xc2v_map.v";
|
||||
} else if (family == "xc3sda") {
|
||||
// Supported block RAMs for Spartan 3A DSP are
|
||||
// a subset of Spartan 6's ones.
|
||||
run("memory_bram -rules +/xilinx/xc3sda_brams.txt");
|
||||
run("techmap -map +/xilinx/xc6s_brams_map.v");
|
||||
params += " -lib +/xilinx/lutrams_xcv.txt";
|
||||
lutrams_map = "+/xilinx/lutrams_xcv_map.v";
|
||||
params += " -lib +/xilinx/brams_xc3sda.txt";
|
||||
brams_map = "+/xilinx/brams_xc3sda_map.v";
|
||||
} else if (family == "xc6s") {
|
||||
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
|
||||
run("techmap -map +/xilinx/xc6s_brams_map.v");
|
||||
params += " -logic-cost-rom 0.015625";
|
||||
params += " -lib +/xilinx/lutrams_xc5v.txt";
|
||||
lutrams_map = "+/xilinx/lutrams_xc5v_map.v";
|
||||
params += " -lib +/xilinx/brams_xc3sda.txt";
|
||||
params += " -D IS_SPARTAN6";
|
||||
brams_map = "+/xilinx/brams_xc3sda_map.v";
|
||||
} else if (family == "xc4v") {
|
||||
params += " -lib +/xilinx/lutrams_xcv.txt";
|
||||
lutrams_map = "+/xilinx/lutrams_xcv_map.v";
|
||||
params += " -lib +/xilinx/brams_xc4v.txt";
|
||||
params += " -D HAS_CASCADE";
|
||||
brams_map = "+/xilinx/brams_xc4v_map.v";
|
||||
} else if (family == "xc5v") {
|
||||
params += " -logic-cost-rom 0.015625";
|
||||
params += " -lib +/xilinx/lutrams_xc5v.txt";
|
||||
lutrams_map = "+/xilinx/lutrams_xc5v_map.v";
|
||||
params += " -lib +/xilinx/brams_xc4v.txt";
|
||||
params += " -D HAS_SIZE_36";
|
||||
params += " -D HAS_CASCADE";
|
||||
brams_map = "+/xilinx/brams_xc5v_map.v";
|
||||
} else if (family == "xc6v" || family == "xc7") {
|
||||
run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
|
||||
run("techmap -map +/xilinx/xc7_brams_map.v");
|
||||
params += " -logic-cost-rom 0.015625";
|
||||
params += " -lib +/xilinx/lutrams_xc5v.txt";
|
||||
lutrams_map = "+/xilinx/lutrams_xc5v_map.v";
|
||||
params += " -lib +/xilinx/brams_xc4v.txt";
|
||||
params += " -D HAS_SIZE_36";
|
||||
params += " -D HAS_CASCADE";
|
||||
params += " -D HAS_CONFLICT_BUG";
|
||||
params += " -D HAS_MIXWIDTH_SDP";
|
||||
brams_map = "+/xilinx/brams_xc6v_map.v";
|
||||
} else if (family == "xcu" || family == "xcup") {
|
||||
run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
|
||||
run("techmap -map +/xilinx/xcu_brams_map.v");
|
||||
} else {
|
||||
log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
|
||||
params += " -logic-cost-rom 0.015625";
|
||||
params += " -lib +/xilinx/lutrams_xcu.txt";
|
||||
lutrams_map = "+/xilinx/lutrams_xc5v_map.v";
|
||||
params += " -lib +/xilinx/brams_xc4v.txt";
|
||||
params += " -D HAS_SIZE_36";
|
||||
params += " -D HAS_MIXWIDTH_SDP";
|
||||
params += " -D HAS_ADDRCE";
|
||||
brams_map = "+/xilinx/brams_xcu_map.v";
|
||||
if (family == "xcup") {
|
||||
params += " -lib +/xilinx/urams.txt";
|
||||
}
|
||||
}
|
||||
if (nolutram)
|
||||
params += " -no-auto-distributed";
|
||||
if (nobram)
|
||||
params += " -no-auto-block";
|
||||
if (!uram)
|
||||
params += " -no-auto-huge";
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("map_lutram", "(skip if '-nolutram')")) {
|
||||
if (!nolutram || help_mode) {
|
||||
run("memory_bram -rules +/xilinx/lut" + lut_size_s + "_lutrams.txt");
|
||||
run("techmap -map +/xilinx/lutrams_map.v");
|
||||
run("memory_libmap" + params);
|
||||
run("techmap -map " + lutrams_map);
|
||||
run("techmap -map " + brams_map);
|
||||
if (family == "xcup") {
|
||||
run("techmap -map +/xilinx/urams_map.v");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,37 @@
|
|||
ram huge $__XILINX_URAM_ {
|
||||
abits 12;
|
||||
width 72;
|
||||
cost 1024;
|
||||
option "BYTEWIDTH" 8 byte 8;
|
||||
option "BYTEWIDTH" 9 byte 9;
|
||||
init zero;
|
||||
port srsw "A" {
|
||||
clock anyedge "C";
|
||||
clken;
|
||||
rdwr no_change;
|
||||
rdinit zero;
|
||||
portoption "RST_MODE" "SYNC" {
|
||||
rdsrst zero ungated;
|
||||
}
|
||||
portoption "RST_MODE" "ASYNC" {
|
||||
rdarst zero;
|
||||
}
|
||||
wrtrans all new;
|
||||
wrbe_separate;
|
||||
}
|
||||
port srsw "B" {
|
||||
clock anyedge "C";
|
||||
clken;
|
||||
rdwr no_change;
|
||||
rdinit zero;
|
||||
portoption "RST_MODE" "SYNC" {
|
||||
rdsrst zero ungated;
|
||||
}
|
||||
portoption "RST_MODE" "ASYNC" {
|
||||
rdarst zero;
|
||||
}
|
||||
wrtrans all old;
|
||||
wrprio "A";
|
||||
wrbe_separate;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
module $__XILINX_URAM_ (...);
|
||||
parameter OPTION_BYTEWIDTH = 8;
|
||||
localparam WR_BE_WIDTH = 72 / OPTION_BYTEWIDTH;
|
||||
|
||||
parameter CLK_C_POL = 1;
|
||||
parameter PORT_A_CLK_POL = 1;
|
||||
parameter PORT_A_OPTION_RST_MODE = "SYNC";
|
||||
parameter PORT_B_CLK_POL = 1;
|
||||
parameter PORT_B_OPTION_RST_MODE = "SYNC";
|
||||
|
||||
input CLK_C;
|
||||
|
||||
input PORT_A_CLK;
|
||||
input PORT_A_CLK_EN;
|
||||
input PORT_A_RD_SRST;
|
||||
input PORT_A_RD_ARST;
|
||||
input PORT_A_WR_EN;
|
||||
input [WR_BE_WIDTH-1:0] PORT_A_WR_BE;
|
||||
input [11:0] PORT_A_ADDR;
|
||||
input [71:0] PORT_A_WR_DATA;
|
||||
output [71:0] PORT_A_RD_DATA;
|
||||
|
||||
input PORT_B_CLK;
|
||||
input PORT_B_CLK_EN;
|
||||
input PORT_B_RD_SRST;
|
||||
input PORT_B_RD_ARST;
|
||||
input PORT_B_WR_EN;
|
||||
input [WR_BE_WIDTH-1:0] PORT_B_WR_BE;
|
||||
input [11:0] PORT_B_ADDR;
|
||||
input [71:0] PORT_B_WR_DATA;
|
||||
output [71:0] PORT_B_RD_DATA;
|
||||
|
||||
wire [71:0] DIN_A, DIN_B, DOUT_A, DOUT_B;
|
||||
|
||||
generate
|
||||
if (OPTION_BYTEWIDTH == 8) begin
|
||||
assign DIN_A = PORT_A_WR_DATA;
|
||||
assign DIN_B = PORT_B_WR_DATA;
|
||||
assign PORT_A_RD_DATA = DOUT_A;
|
||||
assign PORT_B_RD_DATA = DOUT_B;
|
||||
end else begin
|
||||
assign DIN_A = {
|
||||
PORT_A_WR_DATA[71],
|
||||
PORT_A_WR_DATA[62],
|
||||
PORT_A_WR_DATA[53],
|
||||
PORT_A_WR_DATA[44],
|
||||
PORT_A_WR_DATA[35],
|
||||
PORT_A_WR_DATA[26],
|
||||
PORT_A_WR_DATA[17],
|
||||
PORT_A_WR_DATA[8],
|
||||
PORT_A_WR_DATA[70:63],
|
||||
PORT_A_WR_DATA[61:54],
|
||||
PORT_A_WR_DATA[52:45],
|
||||
PORT_A_WR_DATA[43:36],
|
||||
PORT_A_WR_DATA[34:27],
|
||||
PORT_A_WR_DATA[25:18],
|
||||
PORT_A_WR_DATA[16:9],
|
||||
PORT_A_WR_DATA[7:0]
|
||||
};
|
||||
assign DIN_B = {
|
||||
PORT_B_WR_DATA[71],
|
||||
PORT_B_WR_DATA[62],
|
||||
PORT_B_WR_DATA[53],
|
||||
PORT_B_WR_DATA[44],
|
||||
PORT_B_WR_DATA[35],
|
||||
PORT_B_WR_DATA[26],
|
||||
PORT_B_WR_DATA[17],
|
||||
PORT_B_WR_DATA[8],
|
||||
PORT_B_WR_DATA[70:63],
|
||||
PORT_B_WR_DATA[61:54],
|
||||
PORT_B_WR_DATA[52:45],
|
||||
PORT_B_WR_DATA[43:36],
|
||||
PORT_B_WR_DATA[34:27],
|
||||
PORT_B_WR_DATA[25:18],
|
||||
PORT_B_WR_DATA[16:9],
|
||||
PORT_B_WR_DATA[7:0]
|
||||
};
|
||||
assign PORT_A_RD_DATA = {
|
||||
DOUT_A[71],
|
||||
DOUT_A[63:56],
|
||||
DOUT_A[70],
|
||||
DOUT_A[55:48],
|
||||
DOUT_A[69],
|
||||
DOUT_A[47:40],
|
||||
DOUT_A[68],
|
||||
DOUT_A[39:32],
|
||||
DOUT_A[67],
|
||||
DOUT_A[31:24],
|
||||
DOUT_A[66],
|
||||
DOUT_A[23:16],
|
||||
DOUT_A[65],
|
||||
DOUT_A[15:8],
|
||||
DOUT_A[64],
|
||||
DOUT_A[7:0]
|
||||
};
|
||||
assign PORT_B_RD_DATA = {
|
||||
DOUT_B[71],
|
||||
DOUT_B[63:56],
|
||||
DOUT_B[70],
|
||||
DOUT_B[55:48],
|
||||
DOUT_B[69],
|
||||
DOUT_B[47:40],
|
||||
DOUT_B[68],
|
||||
DOUT_B[39:32],
|
||||
DOUT_B[67],
|
||||
DOUT_B[31:24],
|
||||
DOUT_B[66],
|
||||
DOUT_B[23:16],
|
||||
DOUT_B[65],
|
||||
DOUT_B[15:8],
|
||||
DOUT_B[64],
|
||||
DOUT_B[7:0]
|
||||
};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
URAM288 #(
|
||||
.BWE_MODE_A(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
|
||||
.BWE_MODE_B(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
|
||||
.EN_AUTO_SLEEP_MODE("FALSE"),
|
||||
.IREG_PRE_A("FALSE"),
|
||||
.IREG_PRE_B("FALSE"),
|
||||
.IS_CLK_INVERTED(!CLK_C_POL),
|
||||
.OREG_A("FALSE"),
|
||||
.OREG_B("FALSE"),
|
||||
.RST_MODE_A(PORT_A_OPTION_RST_MODE),
|
||||
.RST_MODE_B(PORT_B_OPTION_RST_MODE),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ADDR_A({11'b0, PORT_A_ADDR}),
|
||||
.BWE_A(PORT_A_WR_BE),
|
||||
.EN_A(PORT_A_CLK_EN),
|
||||
.RDB_WR_A(PORT_A_WR_EN),
|
||||
.INJECT_DBITERR_A(1'b0),
|
||||
.INJECT_SBITERR_A(1'b0),
|
||||
.RST_A(PORT_A_OPTION_RST_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
|
||||
.DIN_A(DIN_A),
|
||||
.DOUT_A(DOUT_A),
|
||||
|
||||
.ADDR_B({11'b0, PORT_B_ADDR}),
|
||||
.BWE_B(PORT_B_WR_BE),
|
||||
.EN_B(PORT_B_CLK_EN),
|
||||
.RDB_WR_B(PORT_B_WR_EN),
|
||||
.INJECT_DBITERR_B(1'b0),
|
||||
.INJECT_SBITERR_B(1'b0),
|
||||
.RST_B(PORT_B_OPTION_RST_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
|
||||
.DIN_B(DIN_B),
|
||||
.DOUT_B(DOUT_B),
|
||||
|
||||
.CLK(CLK_C),
|
||||
.SLEEP(1'b0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
# Virtex 2, Virtex 2 Pro, Spartan 3, Spartan 3E block RAM rules.
|
||||
|
||||
bram $__XILINX_RAMB16
|
||||
init 1
|
||||
abits 9 @a9d36
|
||||
dbits 36 @a9d36
|
||||
abits 10 @a10d18
|
||||
dbits 18 @a10d18
|
||||
abits 11 @a11d9
|
||||
dbits 9 @a11d9
|
||||
abits 12 @a12d4
|
||||
dbits 4 @a12d4
|
||||
abits 13 @a13d2
|
||||
dbits 2 @a13d2
|
||||
abits 14 @a14d1
|
||||
dbits 1 @a14d1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 1
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
match $__XILINX_RAMB16
|
||||
min bits 4096
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
|
|
@ -1,266 +0,0 @@
|
|||
// Virtex 2, Virtex 2 Pro, Spartan 3, Spartan 3E, Spartan 3A block RAM
|
||||
// mapping (Spartan 3A is a superset of the other four).
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB16 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 9;
|
||||
parameter CFG_DBITS = 36;
|
||||
parameter CFG_ENABLE_B = 1;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
generate if (CFG_DBITS == 1) begin
|
||||
wire DOB;
|
||||
RAMB16_S1_S1 #(
|
||||
`include "brams_init_16.vh"
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(1'd0),
|
||||
.DOA(A1DATA),
|
||||
.ADDRA(A1ADDR),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.SSRA(|0),
|
||||
.WEA(1'b0),
|
||||
|
||||
.DIB(B1DATA),
|
||||
.DOB(DOB),
|
||||
.ADDRB(B1ADDR),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.SSRB(|0),
|
||||
.WEB(B1EN)
|
||||
);
|
||||
end else if (CFG_DBITS == 2) begin
|
||||
wire [1:0] DOB;
|
||||
RAMB16_S2_S2 #(
|
||||
`include "brams_init_16.vh"
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(2'd0),
|
||||
.DOA(A1DATA),
|
||||
.ADDRA(A1ADDR),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.SSRA(|0),
|
||||
.WEA(1'b0),
|
||||
|
||||
.DIB(B1DATA),
|
||||
.DOB(DOB),
|
||||
.ADDRB(B1ADDR),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.SSRB(|0),
|
||||
.WEB(B1EN)
|
||||
);
|
||||
end else if (CFG_DBITS == 4) begin
|
||||
wire [3:0] DOB;
|
||||
RAMB16_S4_S4 #(
|
||||
`include "brams_init_16.vh"
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(4'd0),
|
||||
.DOA(A1DATA),
|
||||
.ADDRA(A1ADDR),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.SSRA(|0),
|
||||
.WEA(1'b0),
|
||||
|
||||
.DIB(B1DATA),
|
||||
.DOB(DOB),
|
||||
.ADDRB(B1ADDR),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.SSRB(|0),
|
||||
.WEB(B1EN)
|
||||
);
|
||||
end else if (CFG_DBITS == 9) begin
|
||||
wire [7:0] DOB;
|
||||
wire DOPB;
|
||||
RAMB16_S9_S9 #(
|
||||
`include "brams_init_18.vh"
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(8'd0),
|
||||
.DIPA(1'd0),
|
||||
.DOA(A1DATA[7:0]),
|
||||
.DOPA(A1DATA[8]),
|
||||
.ADDRA(A1ADDR),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.SSRA(|0),
|
||||
.WEA(1'b0),
|
||||
|
||||
.DIB(B1DATA[7:0]),
|
||||
.DIPB(B1DATA[8]),
|
||||
.DOB(DOB),
|
||||
.DOPB(DOPB),
|
||||
.ADDRB(B1ADDR),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.SSRB(|0),
|
||||
.WEB(B1EN)
|
||||
);
|
||||
end else if (CFG_DBITS == 18) begin
|
||||
wire [15:0] DOB;
|
||||
wire [1:0] DOPB;
|
||||
RAMB16_S18_S18 #(
|
||||
`include "brams_init_18.vh"
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(16'd0),
|
||||
.DIPA(2'd0),
|
||||
.DOA({A1DATA[16:9], A1DATA[7:0]}),
|
||||
.DOPA({A1DATA[17], A1DATA[8]}),
|
||||
.ADDRA(A1ADDR),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.SSRA(|0),
|
||||
.WEA(1'b0),
|
||||
|
||||
.DIB({B1DATA[16:9], B1DATA[7:0]}),
|
||||
.DIPB({B1DATA[17], B1DATA[8]}),
|
||||
.DOB(DOB),
|
||||
.DOPB(DOPB),
|
||||
.ADDRB(B1ADDR),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.SSRB(|0),
|
||||
.WEB(B1EN)
|
||||
);
|
||||
end else if (CFG_DBITS == 36) begin
|
||||
wire [31:0] DOB;
|
||||
wire [3:0] DOPB;
|
||||
RAMB16_S36_S36 #(
|
||||
`include "brams_init_18.vh"
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(32'd0),
|
||||
.DIPA(4'd0),
|
||||
.DOA({A1DATA[34:27], A1DATA[25:18], A1DATA[16:9], A1DATA[7:0]}),
|
||||
.DOPA({A1DATA[35], A1DATA[26], A1DATA[17], A1DATA[8]}),
|
||||
.ADDRA(A1ADDR),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.SSRA(|0),
|
||||
.WEA(1'b0),
|
||||
|
||||
.DIB({B1DATA[34:27], B1DATA[25:18], B1DATA[16:9], B1DATA[7:0]}),
|
||||
.DIPB({B1DATA[35], B1DATA[26], B1DATA[17], B1DATA[8]}),
|
||||
.DOB(DOB),
|
||||
.DOPB(DOPB),
|
||||
.ADDRB(B1ADDR),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.SSRB(|0),
|
||||
.WEB(B1EN)
|
||||
);
|
||||
end else begin
|
||||
$error("Strange block RAM data width.");
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
|
||||
// Version with separate byte enables, only available on Spartan 3A.
|
||||
|
||||
module \$__XILINX_RAMB16BWE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 9;
|
||||
parameter CFG_DBITS = 36;
|
||||
parameter CFG_ENABLE_B = 4;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
generate if (CFG_DBITS == 18) begin
|
||||
wire [15:0] DOB;
|
||||
wire [1:0] DOPB;
|
||||
RAMB16BWE_S18_S18 #(
|
||||
`include "brams_init_18.vh"
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(16'd0),
|
||||
.DIPA(2'd0),
|
||||
.DOA({A1DATA[16:9], A1DATA[7:0]}),
|
||||
.DOPA({A1DATA[17], A1DATA[8]}),
|
||||
.ADDRA(A1ADDR),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.SSRA(|0),
|
||||
.WEA(2'b00),
|
||||
|
||||
.DIB({B1DATA[16:9], B1DATA[7:0]}),
|
||||
.DIPB({B1DATA[17], B1DATA[8]}),
|
||||
.DOB(DOB),
|
||||
.DOPB(DOPB),
|
||||
.ADDRB(B1ADDR),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.SSRB(|0),
|
||||
.WEB(B1EN)
|
||||
);
|
||||
end else if (CFG_DBITS == 36) begin
|
||||
wire [31:0] DOB;
|
||||
wire [3:0] DOPB;
|
||||
RAMB16BWE_S36_S36 #(
|
||||
`include "brams_init_18.vh"
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(32'd0),
|
||||
.DIPA(4'd0),
|
||||
.DOA({A1DATA[34:27], A1DATA[25:18], A1DATA[16:9], A1DATA[7:0]}),
|
||||
.DOPA({A1DATA[35], A1DATA[26], A1DATA[17], A1DATA[8]}),
|
||||
.ADDRA(A1ADDR),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.SSRA(|0),
|
||||
.WEA(4'b0000),
|
||||
|
||||
.DIB({B1DATA[34:27], B1DATA[25:18], B1DATA[16:9], B1DATA[7:0]}),
|
||||
.DIPB({B1DATA[35], B1DATA[26], B1DATA[17], B1DATA[8]}),
|
||||
.DOB(DOB),
|
||||
.DOPB(DOPB),
|
||||
.ADDRB(B1ADDR),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.SSRB(|0),
|
||||
.WEB(B1EN)
|
||||
);
|
||||
end else begin
|
||||
$error("Strange block RAM data width.");
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
# Spartan 3A block RAM rules.
|
||||
|
||||
bram $__XILINX_RAMB16
|
||||
init 1
|
||||
abits 11 @a11d9
|
||||
dbits 9 @a11d9
|
||||
abits 12 @a12d4
|
||||
dbits 4 @a12d4
|
||||
abits 13 @a13d2
|
||||
dbits 2 @a13d2
|
||||
abits 14 @a14d1
|
||||
dbits 1 @a14d1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 1
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAMB16BWE
|
||||
init 1
|
||||
abits 9 @a9d36
|
||||
dbits 36 @a9d36
|
||||
abits 10 @a10d18
|
||||
dbits 18 @a10d18
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 4 @a9d36
|
||||
enable 1 2 @a10d18
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
match $__XILINX_RAMB16
|
||||
min bits 4096
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB16BWE
|
||||
min bits 4096
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
# Spartan 3A DSP block RAM rules.
|
||||
|
||||
bram $__XILINX_RAMB16BWER_TDP
|
||||
init 1
|
||||
abits 9 @a9d36
|
||||
dbits 36 @a9d36
|
||||
abits 10 @a10d18
|
||||
dbits 18 @a10d18
|
||||
abits 11 @a11d9
|
||||
dbits 9 @a11d9
|
||||
abits 12 @a12d4
|
||||
dbits 4 @a12d4
|
||||
abits 13 @a13d2
|
||||
dbits 2 @a13d2
|
||||
abits 14 @a14d1
|
||||
dbits 1 @a14d1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 4 @a9d36
|
||||
enable 1 2 @a10d18
|
||||
enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
match $__XILINX_RAMB16BWER_TDP
|
||||
min bits 4096
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
# Spartan 6 block RAM rules.
|
||||
|
||||
bram $__XILINX_RAMB8BWER_SDP
|
||||
init 1
|
||||
abits 8
|
||||
dbits 36
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 4
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAMB16BWER_TDP
|
||||
init 1
|
||||
abits 9 @a9d36
|
||||
dbits 36 @a9d36
|
||||
abits 10 @a10d18
|
||||
dbits 18 @a10d18
|
||||
abits 11 @a11d9
|
||||
dbits 9 @a11d9
|
||||
abits 12 @a12d4
|
||||
dbits 4 @a12d4
|
||||
abits 13 @a13d2
|
||||
dbits 2 @a13d2
|
||||
abits 14 @a14d1
|
||||
dbits 1 @a14d1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 4 @a9d36
|
||||
enable 1 2 @a10d18
|
||||
enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAMB8BWER_TDP
|
||||
init 1
|
||||
abits 9 @a9d18
|
||||
dbits 18 @a9d18
|
||||
abits 10 @a10d9
|
||||
dbits 9 @a10d9
|
||||
abits 11 @a11d4
|
||||
dbits 4 @a11d4
|
||||
abits 12 @a12d2
|
||||
dbits 2 @a12d2
|
||||
abits 13 @a13d1
|
||||
dbits 1 @a13d1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 2 @a9d18
|
||||
enable 1 1 @a10d9 @a11d4 @a12d2 @a13d1
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
match $__XILINX_RAMB8BWER_SDP
|
||||
min bits 4096
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB16BWER_TDP
|
||||
min bits 4096
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB8BWER_TDP
|
||||
min bits 4096
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
// Spartan 3A DSP and Spartan 6 block RAM mapping (Spartan 6 is a superset of
|
||||
// Spartan 3A DSP).
|
||||
|
||||
module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [9215:0] INIT = 9216'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [7:0] A1ADDR;
|
||||
output [35:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [7:0] B1ADDR;
|
||||
input [35:0] B1DATA;
|
||||
input [3:0] B1EN;
|
||||
|
||||
wire [12:0] A1ADDR_13 = {A1ADDR, 5'b0};
|
||||
wire [12:0] B1ADDR_13 = {B1ADDR, 5'b0};
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB8BWER #(
|
||||
.RAM_MODE("SDP"),
|
||||
.DATA_WIDTH_A(36),
|
||||
.DATA_WIDTH_B(36),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
`include "brams_init_9.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOBDO(DO[31:16]),
|
||||
.DOADO(DO[15:0]),
|
||||
.DOPBDOP(DOP[3:2]),
|
||||
.DOPADOP(DOP[1:0]),
|
||||
.DIBDI(DI[31:16]),
|
||||
.DIADI(DI[15:0]),
|
||||
.DIPBDIP(DIP[3:2]),
|
||||
.DIPADIP(DIP[1:0]),
|
||||
.WEBWEU(B1EN[3:2]),
|
||||
.WEAWEL(B1EN[1:0]),
|
||||
|
||||
.ADDRAWRADDR(B1ADDR_13),
|
||||
.CLKAWRCLK(CLK3 ^ !CLKPOL3),
|
||||
.ENAWREN(|1),
|
||||
.REGCEA(|0),
|
||||
.RSTA(|0),
|
||||
|
||||
.ADDRBRDADDR(A1ADDR_13),
|
||||
.CLKBRDCLK(CLK2 ^ !CLKPOL2),
|
||||
.ENBRDEN(A1EN),
|
||||
.REGCEBREGCE(|1),
|
||||
.RSTBRST(|0)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB16BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 9;
|
||||
parameter CFG_DBITS = 36;
|
||||
parameter CFG_ENABLE_B = 4;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
|
||||
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
|
||||
wire [3:0] B1EN_4 = {4{B1EN}};
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
wire [31:0] DOB;
|
||||
wire [3:0] DOPB;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB16BWER #(
|
||||
.DATA_WIDTH_A(CFG_DBITS),
|
||||
.DATA_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
`include "brams_init_18.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(32'd0),
|
||||
.DIPA(4'd0),
|
||||
.DOA(DO[31:0]),
|
||||
.DOPA(DOP[3:0]),
|
||||
.ADDRA(A1ADDR_14),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.REGCEA(|1),
|
||||
.RSTA(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DIB(DI),
|
||||
.DIPB(DIP),
|
||||
.DOB(DOB),
|
||||
.DOPB(DOPB),
|
||||
.ADDRB(B1ADDR_14),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTB(|0),
|
||||
.WEB(B1EN_4)
|
||||
);
|
||||
end else begin
|
||||
RAMB16BWER #(
|
||||
.DATA_WIDTH_A(CFG_DBITS),
|
||||
.DATA_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
`include "brams_init_16.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIA(32'd0),
|
||||
.DIPA(4'd0),
|
||||
.DOA(DO[31:0]),
|
||||
.DOPA(DOP[3:0]),
|
||||
.ADDRA(A1ADDR_14),
|
||||
.CLKA(CLK2 ^ !CLKPOL2),
|
||||
.ENA(A1EN),
|
||||
.REGCEA(|1),
|
||||
.RSTA(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DIB(DI),
|
||||
.DIPB(DIP),
|
||||
.DOB(DOB),
|
||||
.DOPB(DOPB),
|
||||
.ADDRB(B1ADDR_14),
|
||||
.CLKB(CLK3 ^ !CLKPOL3),
|
||||
.ENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTB(|0),
|
||||
.WEB(B1EN_4)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 9;
|
||||
parameter CFG_DBITS = 18;
|
||||
parameter CFG_ENABLE_B = 2;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [9215:0] INIT = 9216'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [12:0] A1ADDR_13 = A1ADDR << (13 - CFG_ABITS);
|
||||
wire [12:0] B1ADDR_13 = B1ADDR << (13 - CFG_ABITS);
|
||||
wire [1:0] B1EN_2 = {2{B1EN}};
|
||||
|
||||
wire [1:0] DIP, DOP;
|
||||
wire [15:0] DI, DO;
|
||||
|
||||
wire [15:0] DOBDO;
|
||||
wire [1:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB8BWER #(
|
||||
.RAM_MODE("TDP"),
|
||||
.DATA_WIDTH_A(CFG_DBITS),
|
||||
.DATA_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
`include "brams_init_9.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(16'b0),
|
||||
.DIPADIP(2'b0),
|
||||
.DOADO(DO),
|
||||
.DOPADOP(DOP),
|
||||
.ADDRAWRADDR(A1ADDR_13),
|
||||
.CLKAWRCLK(CLK2 ^ !CLKPOL2),
|
||||
.ENAWREN(A1EN),
|
||||
.REGCEA(|1),
|
||||
.RSTA(|0),
|
||||
.WEAWEL(2'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.DOBDO(DOBDO),
|
||||
.DOPBDOP(DOPBDOP),
|
||||
.ADDRBRDADDR(B1ADDR_13),
|
||||
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
|
||||
.ENBRDEN(|1),
|
||||
.REGCEBREGCE(|0),
|
||||
.RSTBRST(|0),
|
||||
.WEBWEU(B1EN_2)
|
||||
);
|
||||
end else begin
|
||||
RAMB8BWER #(
|
||||
.RAM_MODE("TDP"),
|
||||
.DATA_WIDTH_A(CFG_DBITS),
|
||||
.DATA_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
`include "brams_init_8.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(16'b0),
|
||||
.DIPADIP(2'b0),
|
||||
.DOADO(DO),
|
||||
.DOPADOP(DOP),
|
||||
.ADDRAWRADDR(A1ADDR_13),
|
||||
.CLKAWRCLK(CLK2 ^ !CLKPOL2),
|
||||
.ENAWREN(A1EN),
|
||||
.REGCEA(|1),
|
||||
.RSTA(|0),
|
||||
.WEAWEL(2'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.DOBDO(DOBDO),
|
||||
.DOPBDOP(DOPBDOP),
|
||||
.ADDRBRDADDR(B1ADDR_13),
|
||||
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
|
||||
.ENBRDEN(|1),
|
||||
.REGCEBREGCE(|0),
|
||||
.RSTBRST(|0),
|
||||
.WEBWEU(B1EN_2)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
|
@ -1,363 +0,0 @@
|
|||
// Virtex 6 and Series 7 block RAM mapping.
|
||||
|
||||
module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [36863:0] INIT = 36864'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [8:0] A1ADDR;
|
||||
output [71:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [8:0] B1ADDR;
|
||||
input [71:0] B1DATA;
|
||||
input [7:0] B1EN;
|
||||
|
||||
// Set highest address bit to 1, as stated in UG473 (v1.14) July 3, 2019
|
||||
wire [15:0] A1ADDR_16 = {1'b1, A1ADDR, 6'b0};
|
||||
wire [15:0] B1ADDR_16 = {1'b1, B1ADDR, 6'b0};
|
||||
|
||||
wire [7:0] DIP, DOP;
|
||||
wire [63:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
|
||||
DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
|
||||
assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
|
||||
DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB36E1 #(
|
||||
.RAM_MODE("SDP"),
|
||||
.READ_WIDTH_A(72),
|
||||
.WRITE_WIDTH_B(72),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_36.vh"
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOBDO(DO[63:32]),
|
||||
.DOADO(DO[31:0]),
|
||||
.DOPBDOP(DOP[7:4]),
|
||||
.DOPADOP(DOP[3:0]),
|
||||
.DIBDI(DI[63:32]),
|
||||
.DIADI(DI[31:0]),
|
||||
.DIPBDIP(DIP[7:4]),
|
||||
.DIPADIP(DIP[3:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [8:0] A1ADDR;
|
||||
output [35:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [8:0] B1ADDR;
|
||||
input [35:0] B1DATA;
|
||||
input [3:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
|
||||
wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB18E1 #(
|
||||
.RAM_MODE("SDP"),
|
||||
.READ_WIDTH_A(36),
|
||||
.WRITE_WIDTH_B(36),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_18.vh"
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOBDO(DO[31:16]),
|
||||
.DOADO(DO[15:0]),
|
||||
.DOPBDOP(DOP[3:2]),
|
||||
.DOPADOP(DOP[1:0]),
|
||||
.DIBDI(DI[31:16]),
|
||||
.DIADI(DI[15:0]),
|
||||
.DIPBDIP(DIP[3:2]),
|
||||
.DIPADIP(DIP[1:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 36;
|
||||
parameter CFG_ENABLE_B = 4;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [36863:0] INIT = 36864'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
// Set highest address bit to 1, as stated in UG473 (v1.14) July 3, 2019
|
||||
wire [15:0] A1ADDR_16 = {1'b1, A1ADDR} << (15 - CFG_ABITS);
|
||||
wire [15:0] B1ADDR_16 = {1'b1, B1ADDR} << (15 - CFG_ABITS);
|
||||
wire [7:0] B1EN_8 = B1EN;
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
wire [31:0] DOBDO;
|
||||
wire [3:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB36E1 #(
|
||||
.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_36.vh"
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(32'd0),
|
||||
.DIPADIP(4'd0),
|
||||
.DOADO(DO[31:0]),
|
||||
.DOPADOP(DOP[3:0]),
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.DOBDO(DOBDO),
|
||||
.DOPBDOP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_8)
|
||||
);
|
||||
end else begin
|
||||
RAMB36E1 #(
|
||||
.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_32.vh"
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(32'd0),
|
||||
.DIPADIP(4'd0),
|
||||
.DOADO(DO[31:0]),
|
||||
.DOPADOP(DOP[3:0]),
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.DOBDO(DOBDO),
|
||||
.DOPBDOP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_8)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 18;
|
||||
parameter CFG_ENABLE_B = 2;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
|
||||
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
|
||||
wire [3:0] B1EN_4 = B1EN;
|
||||
|
||||
wire [1:0] DIP, DOP;
|
||||
wire [15:0] DI, DO;
|
||||
|
||||
wire [15:0] DOBDO;
|
||||
wire [1:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB18E1 #(
|
||||
.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_18.vh"
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(16'b0),
|
||||
.DIPADIP(2'b0),
|
||||
.DOADO(DO),
|
||||
.DOPADOP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.DOBDO(DOBDO),
|
||||
.DOPBDOP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_4)
|
||||
);
|
||||
end else begin
|
||||
RAMB18E1 #(
|
||||
.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_16.vh"
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DIADI(16'b0),
|
||||
.DIPADIP(2'b0),
|
||||
.DOADO(DO),
|
||||
.DOPADOP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DIBDI(DI),
|
||||
.DIPBDIP(DIP),
|
||||
.DOBDO(DOBDO),
|
||||
.DOPBDOP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_4)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,151 +0,0 @@
|
|||
# Virtex 6, Series 7, Ultrascale, Ultrascale Plus block RAM rules.
|
||||
|
||||
bram $__XILINX_RAMB36_SDP
|
||||
init 1
|
||||
abits 9
|
||||
dbits 72
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 8
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAMB18_SDP
|
||||
init 1
|
||||
abits 9
|
||||
dbits 36
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 4
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAMB36_TDP
|
||||
init 1
|
||||
abits 10 @a10d36
|
||||
dbits 36 @a10d36
|
||||
abits 11 @a11d18
|
||||
dbits 18 @a11d18
|
||||
abits 12 @a12d9
|
||||
dbits 9 @a12d9
|
||||
abits 13 @a13d4
|
||||
dbits 4 @a13d4
|
||||
abits 14 @a14d2
|
||||
dbits 2 @a14d2
|
||||
abits 15 @a15d1
|
||||
dbits 1 @a15d1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 4 @a10d36
|
||||
enable 1 2 @a11d18
|
||||
enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAMB18_TDP
|
||||
init 1
|
||||
abits 10 @a10d18
|
||||
dbits 18 @a10d18
|
||||
abits 11 @a11d9
|
||||
dbits 9 @a11d9
|
||||
abits 12 @a12d4
|
||||
dbits 4 @a12d4
|
||||
abits 13 @a13d2
|
||||
dbits 2 @a13d2
|
||||
abits 14 @a14d1
|
||||
dbits 1 @a14d1
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 2 @a10d18
|
||||
enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
|
||||
transp 0 0
|
||||
clocks 2 3
|
||||
clkpol 2 3
|
||||
endbram
|
||||
|
||||
# The "min bits" value were taken from:
|
||||
# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
|
||||
# v1.14 ed., p 29-30, July, 2019.
|
||||
# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
|
||||
|
||||
match $__XILINX_RAMB36_SDP
|
||||
attribute !ram_style
|
||||
attribute !logic_block
|
||||
min bits 1024
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB36_SDP
|
||||
attribute ram_style=block ram_block
|
||||
attribute !logic_block
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB18_SDP
|
||||
attribute !ram_style
|
||||
attribute !logic_block
|
||||
min bits 1024
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB18_SDP
|
||||
attribute ram_style=block ram_block
|
||||
attribute !logic_block
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB36_TDP
|
||||
attribute !ram_style
|
||||
attribute !logic_block
|
||||
min bits 1024
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB36_TDP
|
||||
attribute ram_style=block ram_block
|
||||
attribute !logic_block
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB18_TDP
|
||||
attribute !ram_style
|
||||
attribute !logic_block
|
||||
min bits 1024
|
||||
min efficiency 5
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAMB18_TDP
|
||||
attribute ram_style=block ram_block
|
||||
attribute !logic_block
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
|
||||
|
|
@ -1,386 +0,0 @@
|
|||
// Ultrascale and Ultrascale Plus block RAM mapping.
|
||||
|
||||
module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [36863:0] INIT = 36864'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [8:0] A1ADDR;
|
||||
output [71:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [8:0] B1ADDR;
|
||||
input [71:0] B1DATA;
|
||||
input [7:0] B1EN;
|
||||
|
||||
wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
|
||||
wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
|
||||
|
||||
wire [7:0] DIP, DOP;
|
||||
wire [63:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
|
||||
DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
|
||||
assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
|
||||
DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(72),
|
||||
.WRITE_WIDTH_B(72),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_36.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOUTBDOUT(DO[63:32]),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPBDOUTP(DOP[7:4]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.DINBDIN(DI[63:32]),
|
||||
.DINADIN(DI[31:0]),
|
||||
.DINPBDINP(DIP[7:4]),
|
||||
.DINPADINP(DIP[3:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|1),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [8:0] A1ADDR;
|
||||
output [35:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [8:0] B1ADDR;
|
||||
input [35:0] B1DATA;
|
||||
input [3:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
|
||||
wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
RAMB18E2 #(
|
||||
.READ_WIDTH_A(36),
|
||||
.WRITE_WIDTH_B(36),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_18.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DOUTBDOUT(DO[31:16]),
|
||||
.DOUTADOUT(DO[15:0]),
|
||||
.DOUTPBDOUTP(DOP[3:2]),
|
||||
.DOUTPADOUTP(DOP[1:0]),
|
||||
.DINBDIN(DI[31:16]),
|
||||
.DINADIN(DI[15:0]),
|
||||
.DINPBDINP(DIP[3:2]),
|
||||
.DINPADINP(DIP[1:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|1),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 36;
|
||||
parameter CFG_ENABLE_B = 4;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [36863:0] INIT = 36864'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
|
||||
wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
|
||||
wire [7:0] B1EN_8 = B1EN;
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
||||
wire [31:0] DOBDO;
|
||||
wire [3:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_36.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(32'hFFFFFFFF),
|
||||
.DINPADINP(4'hF),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_8),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end else begin
|
||||
RAMB36E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_32.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(32'hFFFFFFFF),
|
||||
.DINPADINP(4'hF),
|
||||
.DOUTADOUT(DO[31:0]),
|
||||
.DOUTPADOUTP(DOP[3:0]),
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_8),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CFG_ABITS = 10;
|
||||
parameter CFG_DBITS = 18;
|
||||
parameter CFG_ENABLE_B = 2;
|
||||
|
||||
parameter CLKPOL2 = 1;
|
||||
parameter CLKPOL3 = 1;
|
||||
parameter [18431:0] INIT = 18432'bx;
|
||||
|
||||
input CLK2;
|
||||
input CLK3;
|
||||
|
||||
input [CFG_ABITS-1:0] A1ADDR;
|
||||
output [CFG_DBITS-1:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [CFG_ABITS-1:0] B1ADDR;
|
||||
input [CFG_DBITS-1:0] B1DATA;
|
||||
input [CFG_ENABLE_B-1:0] B1EN;
|
||||
|
||||
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
|
||||
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
|
||||
wire [3:0] B1EN_4 = B1EN;
|
||||
|
||||
wire [1:0] DIP, DOP;
|
||||
wire [15:0] DI, DO;
|
||||
|
||||
wire [15:0] DOBDO;
|
||||
wire [1:0] DOPBDOP;
|
||||
|
||||
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
|
||||
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
|
||||
|
||||
generate if (CFG_DBITS > 8) begin
|
||||
RAMB18E2 #(
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_18.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(16'hFFFF),
|
||||
.DINPADINP(2'b11),
|
||||
.DOUTADOUT(DO),
|
||||
.DOUTPADOUTP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_4),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end else begin
|
||||
RAMB18E2 #(
|
||||
//.RAM_MODE("TDP"),
|
||||
.READ_WIDTH_A(CFG_DBITS),
|
||||
.READ_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_WIDTH_A(CFG_DBITS),
|
||||
.WRITE_WIDTH_B(CFG_DBITS),
|
||||
.WRITE_MODE_A("READ_FIRST"),
|
||||
.WRITE_MODE_B("READ_FIRST"),
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
|
||||
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
|
||||
`include "brams_init_16.vh"
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DINADIN(16'hFFFF),
|
||||
.DINPADINP(2'b11),
|
||||
.DOUTADOUT(DO),
|
||||
.DOUTPADOUTP(DOP),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLK2),
|
||||
.ENARDEN(A1EN),
|
||||
.ADDRENA(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.DINBDIN(DI),
|
||||
.DINPBDINP(DIP),
|
||||
.DOUTBDOUT(DOBDO),
|
||||
.DOUTPBDOUTP(DOPBDOP),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLK3),
|
||||
.ENBWREN(|1),
|
||||
.ADDRENB(|1),
|
||||
.REGCEB(|0),
|
||||
.RSTRAMB(|0),
|
||||
.RSTREGB(|0),
|
||||
.WEBWE(B1EN_4),
|
||||
|
||||
.SLEEP(|0)
|
||||
);
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
bram $__XILINX_URAM288
|
||||
init 0
|
||||
abits 12
|
||||
dbits 72
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 1 9
|
||||
transp 0 0
|
||||
clocks 2 2
|
||||
clkpol 2 2
|
||||
endbram
|
||||
|
||||
match $__XILINX_URAM288
|
||||
min bits 131072
|
||||
min efficiency 15
|
||||
shuffle_enable B
|
||||
make_transp
|
||||
endmatch
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
module \$__XILINX_URAM288 (CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
|
||||
parameter CLKPOL2 = 1;
|
||||
|
||||
input CLK2;
|
||||
|
||||
input [11:0] A1ADDR;
|
||||
output [71:0] A1DATA;
|
||||
input A1EN;
|
||||
|
||||
input [11:0] B1ADDR;
|
||||
input [71:0] B1DATA;
|
||||
input [8:0] B1EN;
|
||||
|
||||
|
||||
URAM288 #(
|
||||
.BWE_MODE_A("PARITY_INDEPENDENT"),
|
||||
.BWE_MODE_B("PARITY_INDEPENDENT"),
|
||||
.EN_AUTO_SLEEP_MODE("FALSE"),
|
||||
.IREG_PRE_A("FALSE"),
|
||||
.IREG_PRE_B("FALSE"),
|
||||
.IS_CLK_INVERTED(!CLKPOL2),
|
||||
.OREG_A("FALSE"),
|
||||
.OREG_B("FALSE")
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.ADDR_A({11'b0, A1ADDR}),
|
||||
.BWE_A(9'b0),
|
||||
.DIN_A(72'b0),
|
||||
.EN_A(A1EN),
|
||||
.RDB_WR_A(1'b0),
|
||||
.INJECT_DBITERR_A(1'b0),
|
||||
.INJECT_SBITERR_A(1'b0),
|
||||
.RST_A(1'b0),
|
||||
.DOUT_A(A1DATA),
|
||||
|
||||
.ADDR_B({11'b0, B1ADDR}),
|
||||
.BWE_B(B1EN),
|
||||
.DIN_B(B1DATA),
|
||||
.EN_B(|B1EN),
|
||||
.RDB_WR_B(1'b1),
|
||||
.INJECT_DBITERR_B(1'b0),
|
||||
.INJECT_SBITERR_B(1'b0),
|
||||
.RST_B(1'b0),
|
||||
|
||||
.CLK(CLK2),
|
||||
.SLEEP(1'b0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -11,7 +11,7 @@ read_verilog ../common/memory_attributes/attributes_test.v
|
|||
hierarchy -top distributed_ram
|
||||
synth_xilinx -top distributed_ram -noiopad
|
||||
cd distributed_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 8 t:RAM32X1D
|
||||
select -assert-count 1 t:RAM32M
|
||||
|
||||
# Set ram_style distributed to blockram memory; will be implemented as distributed
|
||||
design -reset
|
||||
|
|
@ -19,7 +19,7 @@ read_verilog ../common/memory_attributes/attributes_test.v
|
|||
setattr -set ram_style "distributed" block_ram/m:*
|
||||
synth_xilinx -top block_ram -noiopad
|
||||
cd block_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 32 t:RAM128X1D
|
||||
select -assert-count 16 t:RAM256X1S
|
||||
|
||||
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
|
||||
design -reset
|
||||
|
|
@ -28,7 +28,6 @@ setattr -set logic_block 1 block_ram/m:*
|
|||
synth_xilinx -top block_ram -noiopad
|
||||
cd block_ram # Constrain all select calls below inside the top module
|
||||
select -assert-count 0 t:RAMB18E1
|
||||
select -assert-count 32 t:RAM128X1D
|
||||
|
||||
# Set ram_style block to a distributed memory; will be implemented as blockram
|
||||
design -reset
|
||||
|
|
@ -36,10 +35,3 @@ read_verilog ../common/memory_attributes/attributes_test.v
|
|||
synth_xilinx -top distributed_ram_manual -noiopad
|
||||
cd distributed_ram_manual # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
|
||||
design -reset
|
||||
read_verilog ../common/memory_attributes/attributes_test.v
|
||||
synth_xilinx -top distributed_ram_manual_syn -noiopad
|
||||
cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
### currently. Checking instance counts instead.
|
||||
# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
|
||||
read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
|
||||
chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp
|
||||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
|
@ -35,7 +35,7 @@ chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
|
|||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 0 t:RAMB18E1
|
||||
select -assert-count 4 t:RAM128X1D
|
||||
select -assert-count 4 t:RAM64M
|
||||
|
||||
# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
|
||||
design -reset
|
||||
|
|
@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1
|
|||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_style "block" m:memory
|
||||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
|
|
@ -58,23 +58,7 @@ select -assert-count 1 t:RAMB18E1
|
|||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory
|
||||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 0 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
|
||||
setattr -set logic_block 1 m:memory
|
||||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
|
|
@ -87,11 +71,3 @@ setattr -set ram_style "block" m:memory
|
|||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/blockram.v
|
||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_xilinx -top sync_ram_sdp -noiopad
|
||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
|
|
|
|||
|
|
@ -33,8 +33,8 @@ design -load postopt
|
|||
cd lutram_1w1r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 8 t:FDRE
|
||||
select -assert-count 8 t:RAM32X1D
|
||||
select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D
|
||||
select -assert-count 1 t:RAM32M
|
||||
select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
|
|
@ -51,10 +51,11 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
|
|||
|
||||
design -load postopt
|
||||
cd lutram_1w1r
|
||||
dump
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 8 t:FDRE
|
||||
select -assert-count 8 t:RAM64X1D
|
||||
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
|
||||
select -assert-count 8 t:RAM64X1S
|
||||
select -assert-none t:BUFG t:FDRE t:RAM64X1S %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
|
|
@ -133,8 +134,8 @@ design -load postopt
|
|||
cd lutram_1w1r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 6 t:FDRE
|
||||
select -assert-count 2 t:RAM64M
|
||||
select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
|
||||
select -assert-count 6 t:RAM64X1S
|
||||
select -assert-none t:BUFG t:FDRE t:RAM64X1S %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
|
|
@ -153,5 +154,5 @@ design -load postopt
|
|||
cd lutram_1w1r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 8 t:FDRE
|
||||
select -assert-count 8 t:RAM16X1D
|
||||
select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
|
||||
select -assert-count 8 t:RAM16X1S
|
||||
select -assert-none t:BUFG t:FDRE t:RAM16X1S %% t:* %D
|
||||
|
|
|
|||
Loading…
Reference in New Issue