riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
8,394 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

147 Commits

Author SHA1 Message Date
Eddie Hung f33abd4eab Remove trailing space 2019-08-30 16:44:11 -07:00
Eddie Hung 295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-30 09:50:20 -07:00
David Shah 6919c0f9b0 Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
Eddie Hung 8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung 9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
Marcin Kościelnicki d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
Eddie Hung e658d472c8 Put attributes above port 2019-08-23 11:31:20 -07:00
Eddie Hung d672b1ddec Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-23 11:26:55 -07:00
Eddie Hung 20f4d191b5 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:24:19 -07:00
Eddie Hung 509c353fe9 Forgot one 2019-08-23 11:23:50 -07:00
Eddie Hung 0d0ad15898 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:23:31 -07:00
Eddie Hung a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Eddie Hung 584c680691 Add abc_arrival to SRL* 2019-08-21 11:27:42 -07:00
Eddie Hung b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Eddie Hung 64d62710de Oops 2019-08-20 20:07:38 -07:00
Eddie Hung c26c556384 xilinx to use abc_map.v with -max_iter 1 2019-08-20 19:47:11 -07:00
Eddie Hung 343039496b Add reference to FD* timing 2019-08-20 18:22:58 -07:00
Eddie Hung 091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung bbab608691 Remove SRL* delays from cells_sim.v 2019-08-20 18:14:40 -07:00
Eddie Hung 808f07630f Wrap LUTRAMs in order to capture comb/seq behaviour 2019-08-20 14:49:11 -07:00
Eddie Hung 0079e9b4a6 Add LUTRAM delays 2019-08-20 13:53:38 -07:00
Eddie Hung be9e4f1b67 Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
Eddie Hung c4d4c6db3f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 12:00:12 -07:00
Eddie Hung 526e081342 Add arrival times for SRL outputs 2019-08-19 15:15:43 -07:00
Eddie Hung d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung 562c9e3624 Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules 2019-08-16 15:40:53 -07:00
Marcin Kościelnicki 3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung ed4b2834ef Add assign PCOUT = P to DSP48E1 2019-08-13 12:19:26 -07:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung 13cc106cf7 Fix copy-pasta typo 2019-08-08 10:44:26 -07:00
David Shah b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah 57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
David Shah fe95807f16 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 13:09:12 +01:00
David Shah c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00
David Shah 7a563d0b92 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 13:23:42 +01:00
Eddie Hung c501aa5ee8 Signedness 2019-07-16 15:54:27 -07:00
Eddie Hung 569cd66764 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-16 14:18:36 -07:00
Eddie Hung 5d1ce04381 Add support for {A,B,P}REG in DSP48E1 2019-07-16 14:05:50 -07:00
David Shah d38df68d26 xilinx: Add correct signed behaviour to DSP48E1 model 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 17:53:08 +01:00
Eddie Hung 20e3d2d9b0 Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim 2019-07-15 11:13:22 -07:00
Marcin Kościelnicki a9efacd01d xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado. 2019-07-11 21:13:12 +02:00
Eddie Hung 09ac274716 Revert "Fix broken MUXFx box, use MUXF7x2 box instead" 
This reverts commit a9a140aa6c.
 2019-07-01 14:01:09 -07:00
Eddie Hung a9a140aa6c Fix broken MUXFx box, use MUXF7x2 box instead 2019-07-01 13:36:27 -07:00
Eddie Hung cf020befeb Fix CARRY4 abc_box_id 2019-06-28 11:28:50 -07:00
Eddie Hung 4ef26d4755 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-28 11:09:42 -07:00
Eddie Hung 9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung dbb8c8caaa Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 20:07:31 -07:00
Eddie Hung b7bef15b16 Add "WE" to dist RAM's abc_scc_break 2019-06-26 19:58:09 -07:00
Eddie Hung 812469aaa3 Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 14:48:35 -07:00
Eddie Hung 4d0014d1b1 Cleanup abc_box_id 2019-06-26 11:23:57 -07:00
Miodrag Milanovic ea0b6258ab Simulation model verilog fix 2019-06-26 18:34:34 +02:00
Eddie Hung 6095357390 Add RAM32X1D box info 2019-06-25 09:34:19 -07:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Eddie Hung e1ba25d79f Add RAM32X1D box info 2019-06-24 22:54:35 -07:00
Eddie Hung 1564eb8b54 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-24 22:48:49 -07:00
Eddie Hung 152e682bd5 Add Xilinx dist RAM as comb boxes 2019-06-24 21:54:01 -07:00
Eddie Hung f1675b88f6 Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux 2019-06-24 16:39:18 -07:00
Eddie Hung efd04880db Add RAM32X1D support 2019-06-24 16:16:50 -07:00
Eddie Hung d54dceb547 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-22 19:44:17 -07:00
Eddie Hung 65c022c257 Remove DFF and RAMD box info for now 2019-06-21 20:41:14 -07:00
Eddie Hung 9abde12110 Add $__XILINX_MUXF78 to preserve entire box 2019-06-21 15:47:42 -07:00
Eddie Hung ee428f73ab Remove WIP ABC9 flop support 2019-06-14 10:37:52 -07:00
Eddie Hung 54379f9872 Disable dist RAM boxes due to comb loop 2019-06-11 12:02:51 -07:00
Eddie Hung 8a708d1fdb Remove #ifndef ABC 2019-06-11 12:02:31 -07:00
Eddie Hung 7166dbe418 Remove abc_flop attributes for now 2019-06-06 14:35:38 -07:00
Eddie Hung 6ed15b7890 Update abc attributes on FD*E_1 2019-06-05 12:33:40 -07:00
Eddie Hung b6e59741ae Typo 2019-06-03 20:21:41 -07:00
Eddie Hung ebcc85b9b8 Fix `ifndef 2019-06-03 12:37:02 -07:00
Eddie Hung 01f71085f2 Add FD*E_1 -> FD*E techmap rules 2019-05-31 18:11:24 -07:00
Eddie Hung 1ad33c3b5a Remove whitebox attribute from DRAMs for now 2019-05-30 13:07:29 -07:00
Eddie Hung fdfc18be91 Carry in/out to be the last input/output for chains to be preserved 2019-05-30 01:23:36 -07:00
Eddie Hung 54e28eb3ea Re-enable lib_whitebox 2019-05-27 23:08:55 -07:00
Eddie Hung 4311b9b583 Blackboxes 2019-05-26 11:32:02 -07:00
Eddie Hung ae89e6ab26 Add whitebox support to DRAM 2019-05-23 08:58:57 -07:00
Eddie Hung ee8435b820 Instead of MUXCY/XORCY use CARRY4 (with timing) 2019-05-21 16:19:45 -07:00
Eddie Hung 79fb291dbe Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
Eddie Hung 13ad19482f Merge remote-tracking branch 'origin' into xc7srl 2019-04-20 10:41:43 -07:00
Keith Rothman 1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-12 09:35:15 -07:00
Keith Rothman e107ccdde8 Fix LUT6_2 definition. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 11:43:19 -07:00
Keith Rothman 5e0339855f Add additional cells sim models for core 7-series primatives. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 09:01:53 -07:00
Eddie Hung f1a8e8a480 Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
Keith Rothman 3e16f75bc6 Revert FF models to include IS_x_INVERTED parameters. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:41:21 -08:00
Keith Rothman 3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Eddie Hung 73ddab6960 Add SRL16 and SRL32 sim models 2019-02-28 13:56:22 -08:00
Clifford Wolf 6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
Clifford Wolf 853e949c0e Disabled (unused) Xilinx tristate buffers 2015-02-04 16:33:59 +01:00
Clifford Wolf 816fe6bbe0 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
Clifford Wolf 909a95182b Fixed xilinx FDSE sim model 2015-01-24 11:03:22 +01:00
Clifford Wolf 7031231145 Added MUXCY and XORCY support to synth_xilinx 2015-01-17 15:39:54 +01:00
Clifford Wolf fd8c8d4fd3 Added FF cells to xilinx/cells_sim.v 2015-01-16 14:59:40 +01:00
Clifford Wolf 38dfc5c580 added minimalistic xilinx sim models 2015-01-08 00:05:11 +01:00