Marcus Comstedt
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c836faae3e
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Add -noautowire option to verilog frontend
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2015-08-01 12:16:54 +02:00 |
Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
Clifford Wolf
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7ff802e199
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Verilog front-end: define `BLACKBOX in -lib mode
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2015-04-19 21:30:46 +02:00 |
Clifford Wolf
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a923a63a89
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Ignore celldefine directive in verilog front-end
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2015-03-25 19:46:12 +01:00 |
Clifford Wolf
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1f1deda888
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Added non-std verilog assume() statement
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2015-02-26 18:47:39 +01:00 |
Clifford Wolf
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dc1a0f06fc
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Parser support for complex delay expressions
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2015-02-20 10:21:36 +01:00 |
Clifford Wolf
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e0e6d130cd
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YosysJS stuff
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2015-02-19 13:36:54 +01:00 |
Clifford Wolf
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7f1a1759d7
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Added "read_verilog -nomeminit" and "nomeminit" attribute
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2015-02-14 11:21:12 +01:00 |
Clifford Wolf
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ef151b0b30
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Fixed handling of "//" in filenames in verilog pre-processor
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2015-02-14 08:41:03 +01:00 |
Clifford Wolf
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4f68a77e3f
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Improved read_verilog support for empty behavioral statements
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2015-02-10 12:17:29 +01:00 |
Clifford Wolf
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df9d096a7d
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Ignoring more system task and functions
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2015-01-15 13:08:19 +01:00 |
Fabio Utzig
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fff6f00b3c
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Enable bison to be customized
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2015-01-08 09:56:20 -02:00 |
Clifford Wolf
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1bd67d792e
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Define YOSYS and SYNTHESIS in preproc
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2015-01-02 17:11:54 +01:00 |
Clifford Wolf
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7751c491fb
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Improved some warning messages
|
2014-12-27 03:40:27 +01:00 |
Clifford Wolf
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1282a113da
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Fixed supply0/supply1 with many wires
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2014-12-11 13:56:20 +01:00 |
Clifford Wolf
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76c83283c4
|
Fixed minor bug in parsing delays
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2014-11-24 14:48:07 +01:00 |
Clifford Wolf
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56c7d1e266
|
Fixed two minor bugs in constant parsing
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2014-11-24 14:39:24 +01:00 |
Clifford Wolf
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87333f3ae2
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Added warning for use of 'z' constants in HDL
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2014-11-14 19:59:50 +01:00 |
Clifford Wolf
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4e5350b409
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Fixed parsing of nested verilog concatenation and replicate
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2014-11-12 19:10:35 +01:00 |
Clifford Wolf
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fe829bdbdc
|
Added log_warning() API
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2014-11-09 10:44:23 +01:00 |
Clifford Wolf
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a21481b338
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Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
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2014-10-30 14:01:02 +01:00 |
Clifford Wolf
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f9c096eeda
|
Added support for task and function args in parentheses
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2014-10-27 13:21:57 +01:00 |
Clifford Wolf
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c5eb5e56b8
|
Re-introduced Yosys::readsome() helper function
(f.read() + f.gcount() made problems with lines > 16kB)
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2014-10-23 10:58:36 +02:00 |
Clifford Wolf
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3838856a9e
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Print "SystemVerilog" in "read_verilog -sv" log messages
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2014-10-16 10:31:54 +02:00 |
Clifford Wolf
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f65e1c309f
|
Updated .gitignore file for ilang and verilog frontends
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2014-10-15 01:14:38 +02:00 |
Clifford Wolf
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c3e9922b5d
|
Replaced readsome() with read() and gcount()
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2014-10-15 01:12:53 +02:00 |
William Speirs
|
fad0b0c506
|
Updated lexers & parsers to include prefixes
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2014-10-15 00:48:19 +02:00 |
Clifford Wolf
|
8263f6a74a
|
Fixed win32 troubles with f.readsome()
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2014-10-11 11:36:22 +02:00 |
Clifford Wolf
|
bbd808072b
|
Added format __attribute__ to stringf()
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2014-10-10 17:22:08 +02:00 |
Clifford Wolf
|
4569a747f8
|
Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
Clifford Wolf
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f9a307a50b
|
namespace Yosys
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2014-09-27 16:17:53 +02:00 |
Clifford Wolf
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58367cd87a
|
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
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2014-08-23 15:14:58 +02:00 |
Clifford Wolf
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19cff41eb4
|
Changed frontend-api from FILE to std::istream
|
2014-08-23 15:03:55 +02:00 |
Clifford Wolf
|
e218f0eacf
|
Added support for non-standard <plugin>:<c_name> DPI syntax
|
2014-08-22 14:30:29 +02:00 |
Clifford Wolf
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6c5cafcd8b
|
Added support for DPI function with different names in C and Verilog
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2014-08-21 17:22:04 +02:00 |
Clifford Wolf
|
7bfc4ae120
|
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
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2014-08-21 12:43:51 +02:00 |
Clifford Wolf
|
38addd4c67
|
Added support for global tasks and functions
|
2014-08-21 12:42:28 +02:00 |
Clifford Wolf
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640d9fc551
|
Added "via_celltype" attribute on task/func
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2014-08-18 14:29:30 +02:00 |
Clifford Wolf
|
6d56172c0d
|
Fixed line numbers when using here-doc macros
|
2014-08-14 22:26:30 +02:00 |
Clifford Wolf
|
f53984795d
|
Added support for non-standard """ macro bodies
|
2014-08-13 13:03:38 +02:00 |
Clifford Wolf
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2dc3333734
|
Also allow "module foobar(input foo, output bar, ...);" syntax
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2014-08-07 16:41:27 +02:00 |
Clifford Wolf
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d259abbda2
|
Added AST_MULTIRANGE (arrays with more than 1 dimension)
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2014-08-06 15:52:54 +02:00 |
Clifford Wolf
|
91dd87e60b
|
Improved scope resolution of local regs in Verilog+AST frontend
|
2014-08-05 12:15:53 +02:00 |
Clifford Wolf
|
b5a3419ac2
|
Added support for non-standard "module mod_name(...);" syntax
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2014-08-04 15:40:07 +02:00 |
Clifford Wolf
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1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
7daad40ca4
|
Fixed counting verilog line numbers for "// synopsys translate_off" sections
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2014-07-30 20:18:48 +02:00 |
Clifford Wolf
|
e605af8a49
|
Fixed Verilog pre-processor for files with no trailing newline
|
2014-07-29 20:14:25 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
b17d6531c8
|
Added "make PRETTY=1"
|
2014-07-24 17:15:01 +02:00 |
Clifford Wolf
|
ee8ad72fd9
|
fixed parsing of constant with comment between size and value
|
2014-07-02 06:27:04 +02:00 |
Clifford Wolf
|
0c4c79c4c6
|
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
|
2014-06-16 15:02:40 +02:00 |
Clifford Wolf
|
7f57bc8385
|
Improved parsing of large integer constants
|
2014-06-15 08:48:17 +02:00 |
Clifford Wolf
|
9bd7d5c468
|
Added handling of real-valued parameters/localparams
|
2014-06-14 12:00:47 +02:00 |
Clifford Wolf
|
7ef0da32cd
|
Added Verilog lexer and parser support for real values
|
2014-06-13 11:29:23 +02:00 |
Clifford Wolf
|
482d9208aa
|
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
|
2014-06-12 11:54:20 +02:00 |
Clifford Wolf
|
e275e8eef9
|
Add support for cell arrays
|
2014-06-07 11:48:50 +02:00 |
Clifford Wolf
|
5281562d0e
|
made the generate..endgenrate keywords optional
|
2014-06-06 23:05:01 +02:00 |
Clifford Wolf
|
b5cd7a0179
|
added while and repeat support to verilog parser
|
2014-06-06 17:40:04 +02:00 |
Clifford Wolf
|
f9c1cd5edb
|
Improved error message for options after front-end filename arguments
|
2014-06-04 09:10:50 +02:00 |
Clifford Wolf
|
7188542155
|
Fixed clang -Wdeprecated-register warnings
|
2014-04-20 14:28:23 +02:00 |
Clifford Wolf
|
a1be4816d6
|
Replaced depricated %name-prefix= bison directive
|
2014-04-20 14:22:11 +02:00 |
Clifford Wolf
|
fad8558eb5
|
Merged OSX fixes from Siesh1oo with some modifications
|
2014-03-13 12:48:10 +01:00 |
Clifford Wolf
|
9992026a8d
|
Added support for `line compiler directive
|
2014-03-11 14:06:57 +01:00 |
Clifford Wolf
|
02e6f2c5be
|
Added Verilog support for "`default_nettype none"
|
2014-02-17 14:28:52 +01:00 |
Clifford Wolf
|
7d7e068dd1
|
Added a warning note about error reporting to read_verilog help message
|
2014-02-16 20:20:25 +01:00 |
Clifford Wolf
|
cd9e8741a7
|
Implemented read_verilog -defer
|
2014-02-13 13:59:13 +01:00 |
Clifford Wolf
|
007bdff55d
|
Added support for functions returning integer
|
2014-02-12 23:29:54 +01:00 |
Clifford Wolf
|
aa8e754ae5
|
Added read_verilog -setattr
|
2014-02-05 11:22:10 +01:00 |
Clifford Wolf
|
cdd6e11af5
|
Added support for blanks after -I and -D in read_verilog
|
2014-02-02 13:06:21 +01:00 |
Clifford Wolf
|
d06258f74f
|
Added constant size expression support of sized constants
|
2014-02-01 13:50:23 +01:00 |
Clifford Wolf
|
375c4dddc1
|
Added read_verilog -icells option
|
2014-01-29 00:59:28 +01:00 |
Clifford Wolf
|
0b47d907d3
|
Fixed handling of unsized constants in verilog frontend
|
2014-01-24 15:05:24 +01:00 |
Clifford Wolf
|
9a1eb45c75
|
Added Verilog parser support for asserts
|
2014-01-19 04:18:22 +01:00 |
Clifford Wolf
|
13359d65ba
|
Fixed parsing of verilog macros at end of line
|
2014-01-18 19:22:20 +01:00 |
Clifford Wolf
|
6170cfe9cd
|
Added verilog_defaults command
|
2014-01-17 17:22:29 +01:00 |
Clifford Wolf
|
1dcbba1abf
|
Fixed parsing of non-arg macro calls followed by "("
|
2013-12-27 16:25:27 +01:00 |
Clifford Wolf
|
72026a934e
|
Fixed parsing of macros with no arguments and expansion text starting with "("
|
2013-12-27 15:05:52 +01:00 |
Clifford Wolf
|
ecc30255ba
|
Added proper === and !== support in constant expressions
|
2013-12-27 13:50:08 +01:00 |
Clifford Wolf
|
fbd06a1afc
|
Added elsif preproc support
|
2013-12-18 13:41:36 +01:00 |
Clifford Wolf
|
921064c200
|
Added support for macro arguments
|
2013-12-18 13:21:02 +01:00 |
Clifford Wolf
|
5c39948ead
|
Added AstNode::mkconst_str API
|
2013-12-05 12:53:49 +01:00 |
Clifford Wolf
|
4a4a3fc337
|
Various improvements in support for generate statements
|
2013-12-04 21:06:54 +01:00 |
Clifford Wolf
|
507c63d112
|
Added support for local regs in named blocks
|
2013-12-04 09:10:16 +01:00 |
Clifford Wolf
|
7d9a90396d
|
Added verilog frontend -ignore_redef option
|
2013-11-24 19:57:42 +01:00 |
Clifford Wolf
|
1de12e1efc
|
Improved handling of initialized registers
|
2013-11-23 16:26:59 +01:00 |
Clifford Wolf
|
295e352ba6
|
Renamed "placeholder" to "blackbox"
|
2013-11-22 15:01:12 +01:00 |
Clifford Wolf
|
a362fd81ae
|
Fixed O(n^2) performance bug in verilog preprocessor
|
2013-11-22 14:08:43 +01:00 |
Clifford Wolf
|
e4429c480e
|
Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
|
2013-11-22 12:46:02 +01:00 |
Clifford Wolf
|
92035fb38e
|
Implemented indexed part selects
|
2013-11-20 13:05:27 +01:00 |
Clifford Wolf
|
0f04738f40
|
Added "synthesis" in (synopsys|synthesis) comment support
|
2013-11-20 11:44:09 +01:00 |
Clifford Wolf
|
19dba2561e
|
Implemented part/bit select on memory read
|
2013-11-20 10:51:32 +01:00 |
Clifford Wolf
|
e340532ce5
|
Added init= attribute for fpga-style reset values
|
2013-11-20 01:49:37 +01:00 |
Clifford Wolf
|
0dfdbd991a
|
Fixed parsing of module arguments when one type is used for many args
|
2013-11-19 20:35:31 +01:00 |
Clifford Wolf
|
63060dcd2e
|
Fixed parsing of "parameter integer"
|
2013-11-13 15:30:23 +01:00 |
Clifford Wolf
|
f050c40519
|
Various fixes for correct parameter support
|
2013-11-07 10:02:11 +01:00 |
Clifford Wolf
|
23cf23418c
|
Fixed handling of boolean attributes (frontends)
|
2013-10-24 11:20:13 +02:00 |
Clifford Wolf
|
eae43e2db4
|
Fixed handling of boolean attributes (kernel)
|
2013-10-24 10:59:27 +02:00 |
Johann Glaser
|
f352205635
|
fixed Verilog parser filename and line numbering issue with include files
|
2013-08-21 09:20:59 +02:00 |
Johann Glaser
|
a99c224157
|
Added support for include directories with the new '-I' argument of the
'read_verilog' command
|
2013-08-20 15:48:16 +02:00 |
Johann Glaser
|
6c4cbc03c2
|
Added support for notif0/notif1 primitives
|
2013-08-20 11:23:59 +02:00 |
Clifford Wolf
|
8656b1c08f
|
Added support for bufif0/bufif1 primitives
|
2013-08-19 19:50:04 +02:00 |
Clifford Wolf
|
4214561890
|
Improved ast dumping (ast/verilog frontend)
|
2013-08-19 19:49:14 +02:00 |
Clifford Wolf
|
00a6c1d9a5
|
Major redesign of expr width/sign detecion (verilog/ast frontend)
|
2013-07-09 14:31:57 +02:00 |
Clifford Wolf
|
56432a920f
|
Added defparam support to Verilog/AST frontend
|
2013-07-04 14:12:33 +02:00 |
Clifford Wolf
|
0c6ffc4c65
|
More fixes for bugs found using xsthammer
|
2013-06-13 11:18:45 +02:00 |
Clifford Wolf
|
4b311b7b99
|
Further improved and extended xsthammer
|
2013-06-11 19:49:35 +02:00 |
Clifford Wolf
|
db98a18edb
|
Enabled AST/Verilog front-end optimizations per default
|
2013-06-10 13:19:04 +02:00 |
Clifford Wolf
|
46fbe9d262
|
Added SAT generator and simple sat_solve command
|
2013-06-07 13:59:13 +02:00 |
Johann Glaser
|
10a195c0a1
|
added option '-Dname[=definition]' to command 'read_verilog'
|
2013-05-19 17:07:52 +02:00 |
Clifford Wolf
|
b56e06d2f5
|
Added support for verilog === operator
|
2013-05-07 14:35:40 +02:00 |
Clifford Wolf
|
161565be10
|
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
|
2013-03-31 11:19:11 +02:00 |
Clifford Wolf
|
7bfc7b61a8
|
Implemented proper handling of stub placeholder modules
|
2013-03-28 09:20:10 +01:00 |
Clifford Wolf
|
7a99349de4
|
Improvements and bugfixes for generate blocks with local signals
|
2013-03-26 11:31:34 +01:00 |
Clifford Wolf
|
df9753d398
|
Added mem2reg option to verilog frontend
|
2013-03-24 11:13:32 +01:00 |
Clifford Wolf
|
e45d1c8865
|
Tiny fixes to verilog parser
|
2013-03-23 18:54:31 +01:00 |
Clifford Wolf
|
8a6b0a3520
|
Added help messages to ilang and verilog frontends
|
2013-03-01 08:03:00 +01:00 |
Clifford Wolf
|
a321a5c412
|
Moved stand-alone libs to libs/ directory and added libs/subcircuit
|
2013-02-27 09:32:19 +01:00 |
Clifford Wolf
|
4f0c2862a0
|
Added support for verilog genblock[index].member syntax
|
2013-02-26 13:18:22 +01:00 |
Clifford Wolf
|
6d1502b948
|
Added support for "always @(*)"
|
2013-01-16 17:32:11 +01:00 |
Clifford Wolf
|
6543917fb8
|
added .gitignore files
|
2013-01-05 11:19:11 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |