Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
b9ff0503f3
synth_xilinx's muxcover call to be very conservative -- -nodecode
2019-06-26 17:57:10 -07:00
Eddie Hung
f0a1726a1a
Accidentally removed "simplemap $mux"
2019-06-26 17:48:49 -07:00
Eddie Hung
2b104ed6c8
Replace with <internal options>
2019-06-26 17:42:50 -07:00
Eddie Hung
cae69a3edd
Rework help_mode for synth_xilinx -widemux
2019-06-26 17:41:21 -07:00
Eddie Hung
5f807a7a5b
Return to upstream synth_xilinx with opt -full and wreduce
2019-06-26 16:25:48 -07:00
Eddie Hung
c762be5930
Instead of blocking wreduce on $mux, use -keepdc instead #1132
2019-06-26 11:48:35 -07:00
Eddie Hung
8d8261c71f
Do not call opt with -full before muxcover
2019-06-26 11:38:28 -07:00
Eddie Hung
80de03a7a6
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 11:24:39 -07:00
Eddie Hung
612083a807
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 10:33:54 -07:00
Eddie Hung
5e1b8d458b
Remove unused var
2019-06-26 10:33:07 -07:00
Eddie Hung
988e6163ab
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
Eddie Hung
799b18263f
Merge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 10:04:01 -07:00
Eddie Hung
7389b043c0
Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux
2019-06-26 09:33:38 -07:00
Eddie Hung
177c26ca35
Rename -minmuxf to -widemux
2019-06-26 09:16:45 -07:00
Eddie Hung
7fbfcf20d1
Move comment
2019-06-24 14:15:00 -07:00
Eddie Hung
aa1eeda567
Modify costs for muxcover
2019-06-24 11:51:55 -07:00
Eddie Hung
36e6da5396
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
Eddie Hung
39e0e006d5
Fix wreduce call (!!!), tweak muxcover costs
2019-06-21 18:12:07 -07:00
Eddie Hung
faa2d6fc1c
Constrain wreduce only if wide mux
2019-06-21 17:12:34 -07:00
Eddie Hung
ed00823b41
synth_xilinx to now wreduce except $mux, remove extra peepopt
2019-06-21 16:56:56 -07:00
Eddie Hung
11886c874c
Restore wreduce to synth_xilinx, after muxcover
2019-06-21 16:18:29 -07:00
Eddie Hung
aa0b107afb
synth_xilinx to use _ABC macro, and perform muxpack again
2019-06-21 15:48:20 -07:00
Eddie Hung
7acbea6b28
Fix alignment
2019-06-21 14:38:30 -07:00
Eddie Hung
f433a52374
Add FIXME about need for -mux4
2019-06-21 11:15:23 -07:00
Eddie Hung
dd22edcd28
Expand synth -coarse without wreduce, move muxcover
2019-06-21 11:12:32 -07:00
Eddie Hung
f11c9a419b
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
2019-06-20 17:38:16 -07:00
Eddie Hung
d1dadfcec8
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
2019-06-20 16:45:09 -07:00
Eddie Hung
5ce672d1c5
Merge remote-tracking branch 'origin/xaig' into xaig_dff
2019-06-17 12:14:55 -07:00
Eddie Hung
c15ee827f4
Try -W 300
2019-06-17 10:29:06 -07:00
Eddie Hung
1ec450d6bf
Try -W 300
2019-06-16 12:08:03 -07:00
Eddie Hung
a76c8a7ffd
Fix initialisation of flops
2019-06-15 09:46:35 -07:00
Eddie Hung
ac18a76beb
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
2019-06-15 09:34:48 -07:00
Eddie Hung
295bb23ae0
Wrap FDRE with $__ABC_FDRE containing comb
2019-06-15 09:08:56 -07:00
Eddie Hung
b63b2a0bd4
Revert "Remove wide mux inference"
...
This reverts commit 738fdfe8f5
.
2019-06-14 12:50:24 -07:00
Eddie Hung
2e34859a6b
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
2019-06-14 11:38:22 -07:00
Eddie Hung
d47ff7ba87
Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
2019-06-14 10:51:11 -07:00
Eddie Hung
627a62a797
Make doc consistent
2019-06-14 10:32:46 -07:00
Eddie Hung
c7f5091c2f
Reduce diff with master
2019-06-12 09:34:41 -07:00
Eddie Hung
99267f660f
Fix spacing
2019-06-12 09:21:52 -07:00
Eddie Hung
738fdfe8f5
Remove wide mux inference
2019-06-12 09:20:46 -07:00
Eddie Hung
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
Eddie Hung
02973474df
Remove extra newline
2019-06-03 20:04:47 -07:00
Eddie Hung
0ad50332d9
Execute techmap and arith_map simultaneously
2019-06-03 19:36:09 -07:00
Clifford Wolf
04ef222cfb
Add "stat -tech xilinx"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:24:52 +02:00
Clifford Wolf
09467bb9a3
Add "synth_xilinx -arch"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 15:04:36 +02:00
Eddie Hung
d394b9301b
Back to passing all xc7srl tests!
2019-05-01 18:23:21 -07:00
Eddie Hung
31ff0d8ef5
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
2019-05-01 18:09:38 -07:00
Marcin Kościelnicki
98e5a625c4
synth_xilinx: Add -nocarry and -nomux options.
2019-04-30 12:54:21 +02:00
Eddie Hung
e97178a888
WIP
2019-04-28 12:51:00 -07:00
Eddie Hung
d855683917
Revert synth_xilinx 'fine' label more to how it used to be...
2019-04-26 16:53:16 -07:00
Eddie Hung
ea0e0722bb
Where did this check come from!?!
2019-04-26 15:35:34 -07:00
Eddie Hung
727eec04c5
Refactor synth_xilinx to auto-generate doc
2019-04-26 14:32:18 -07:00
Eddie Hung
0bd2bfa737
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 18:15:28 -07:00
Eddie Hung
ec88129a5c
Update help message
2019-04-22 11:38:23 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Eddie Hung
0e76718720
Move 'shregmap -tech xilinx' into map_cells
2019-04-22 10:45:39 -07:00
Eddie Hung
e300b1922c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 10:36:27 -07:00
Clifford Wolf
cf1ba46fa0
Re-added clean after techmap in synth_xilinx
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 09:03:11 +02:00
Eddie Hung
d342b5b135
Tidy up, fix for -nosrl
2019-04-21 15:33:03 -07:00
Eddie Hung
726e2da8f2
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-21 14:28:55 -07:00
Eddie Hung
a3371e118b
Merge branch 'master' into map_cells_before_map_luts
2019-04-21 14:24:50 -07:00
Eddie Hung
ae95aba60a
Add comments
2019-04-21 14:16:59 -07:00
Eddie Hung
d99422411f
Use new pmux2shiftx from #944 , remove my old attempt
2019-04-21 14:16:34 -07:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Eddie Hung
6008bb7002
Revert "synth_* with -retime option now calls abc with -D 1 as well"
...
This reverts commit 9a6da9a79a
.
2019-04-18 07:59:16 -07:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Eddie Hung
9a6da9a79a
synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
a5f33b5409
Move dffinit til after abc
2019-04-05 16:20:43 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
9758701574
Move techamp t:$_DFF_?N? to before abc call
2019-04-05 15:39:05 -07:00
Eddie Hung
8b6085254a
Resolve @daveshah1 comment, update synth_xilinx help
2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
2019-04-05 14:43:06 -07:00
Eddie Hung
544843da71
techmap inside map_cells stage
2019-04-05 12:55:52 -07:00
Eddie Hung
7b7ddbdba7
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 08:13:34 -07:00
Eddie Hung
e3f20b17af
Missing techmap entry in help
2019-04-04 08:13:10 -07:00
Eddie Hung
572603409c
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 07:54:42 -07:00
Eddie Hung
d9cb787391
synth_xilinx to map_cells before map_luts
2019-04-04 07:48:13 -07:00
Eddie Hung
736e19f02d
t:$dff* -> t:$dff t:$dffe
2019-04-04 07:39:19 -07:00
Eddie Hung
0e2d929cea
-nosrl meant when -nobram
2019-04-03 08:28:07 -07:00
Eddie Hung
88630cd02c
Disable shregmap in synth_xilinx if -retime
2019-04-03 07:14:20 -07:00
Eddie Hung
f9fb05cf66
synth_xilinx to use shregmap with -minlen 3
2019-03-25 13:18:55 -07:00
Eddie Hung
4cc6b3e942
Add '-nosrl' option to synth_xilinx
2019-03-21 15:04:44 -07:00
Eddie Hung
ae2a625d05
Restore original synth_xilinx commands
2019-03-19 16:14:08 -07:00
Eddie Hung
24553326dd
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 13:11:30 -07:00
Clifford Wolf
fe1fb1336b
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-19 20:30:28 +01:00
Eddie Hung
29a8d4745e
Cleanup synth_xilinx
2019-03-15 23:01:40 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Eddie Hung
af5706c2a3
Misspell
2019-03-14 09:06:56 -07:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
...
This reverts commit 26ecbc1aee
.
2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Eddie Hung
edca2f1163
Move shregmap until after first techmap
2019-03-13 17:13:52 -07:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream
...
Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
Clifford Wolf
13844c7658
Use "write_edif -pvector bra" for Xilinx EDIF files
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 15:16:13 -08:00
Keith Rothman
5ebeca12eb
Use singular for disabling of DRAM or BRAM inference.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8
Modify arguments to match existing style.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54
Changes required for VPR place and route synth_xilinx.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:02:27 -08:00
Eddie Hung
fe4d6898de
synth_xilinx to call shregmap with enable support
2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0
synth_xilinx to use shregmap with -params too
2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a
synth_xilinx to now have shregmap call after dff2dffe
2019-02-28 09:32:29 -08:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Tim 'mithro' Ansell
b111ea1228
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
...
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
2018-10-08 16:52:12 -07:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
...
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Clifford Wolf
6991c132b5
Add Xilinx RAM64X1D and RAM128X1D simulation models
2018-03-07 17:31:48 +01:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
ff5c61b120
Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
Clifford Wolf
a75f94ec4a
Run dffsr2dff in synth_xilinx
2016-02-13 08:20:19 +01:00
Clifford Wolf
17372d8abd
Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00
Clifford Wolf
864808992b
Bugfix in Xilinx LUT mapping
2015-10-30 13:58:03 +01:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
c329233f0d
Added output args to synth_ice40
2015-05-26 17:08:53 +02:00
Clifford Wolf
b00cad81d7
Towards DRAM support in Xilinx flow
2015-04-09 08:17:14 +02:00
Clifford Wolf
4389d9306e
Added Xilinx bram black-box modules
2015-04-06 08:44:30 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
4d34d031f9
Added "stat" to "synth" and "synth_xilinx"
2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9
Added final checks to "synth" and "synth_xilinx"
2015-02-15 13:00:00 +01:00
Clifford Wolf
bebbf2e5a4
no support for 6-series xilinx devices
2015-02-01 23:06:44 +01:00
Clifford Wolf
816fe6bbe0
Added Xilinx example for Basys3 board
2015-02-01 17:09:34 +01:00
Clifford Wolf
d29d26f882
Various cleanups in xilinx techlib
2015-01-18 19:43:54 +01:00
Clifford Wolf
279a18c9a3
Added synth_xilinx -retime -flatten
2015-01-17 20:47:18 +01:00
Clifford Wolf
7031231145
Added MUXCY and XORCY support to synth_xilinx
2015-01-17 15:39:54 +01:00
Clifford Wolf
dff8bd3b2a
Added dff2dffe to synth_xilinx
2015-01-16 15:49:15 +01:00
Clifford Wolf
b197279f3c
Added Xilinx MUXF7 and MUXF8 support
2015-01-15 13:50:04 +01:00
Clifford Wolf
153d3dd4e0
Various cleanups in synth_xilinx command
2015-01-13 13:20:32 +01:00
Clifford Wolf
4a0b3a5423
Various small improvements to synth_xilinx
2015-01-06 14:37:50 +01:00
Clifford Wolf
9ea2511fe8
Towards Xilinx bram support
2015-01-05 13:59:04 +01:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
20175afd29
Added "techmap -share_map" option
2013-11-24 19:50:25 +01:00
Clifford Wolf
4a3669d871
Added synth_xilinx command
2013-10-27 09:51:06 +01:00