riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,744 Commits 85 Branches 48 Tags 64 MiB
Commit Graph

799 Commits

Author SHA1 Message Date
Miodrag Milanovic 3de7889d08 Separate check for ff's types 2019-10-04 12:48:27 +02:00
Miodrag Milanovic 286a272872 Cleaned tests 2019-10-04 12:42:06 +02:00
Miodrag Milanovic f94dc2c072 Remove not needed tests 2019-10-04 12:41:41 +02:00
Miodrag Milanovic ef417fb1b3 Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix 2019-10-04 12:20:49 +02:00
Miodrag Milanovic 03a3deec43 Cleanup and formating 2019-10-04 11:09:59 +02:00
Miodrag Milanovic a5844e3ceb split latches into separate checks 2019-10-04 11:08:42 +02:00
Miodrag Milanovic 3238ee7d35 check muxes per type 2019-10-04 11:04:18 +02:00
Miodrag Milanovic 91ad3ab717 check ff's separately 2019-10-04 11:00:49 +02:00
Miodrag Milanovic 3d3479b0af Cleanup top modules and not used defines 2019-10-04 10:57:47 +02:00
Miodrag Milanovic 1435b9bf97 remove alu test 2019-10-04 10:55:13 +02:00
Miodrag Milanovic b932654964 Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic 2019-10-04 10:52:16 +02:00
Miodrag Milanovic 7785f23719 Check latches type one by one 2019-10-04 10:31:51 +02:00
Miodrag Milanovic 3358b2f185 Removed top module where not needed 2019-10-04 09:53:54 +02:00
Miodrag Milanovic 3c40c81030 Test muxes synth one by one 2019-10-04 08:52:54 +02:00
Miodrag Milanovic d6ef9b1a6b Cleaned verilog code from not used defines 2019-10-04 08:45:58 +02:00
Miodrag Milanovic abb5a3a44d Check for MULT18X18D, since that is working now 2019-10-04 08:44:10 +02:00
Miodrag Milanovic 9e8175fc75 Check flops one by one 2019-10-04 08:42:29 +02:00
Miodrag Milanovic d19f765a58 Removed alu and div_mod tests as agreed 2019-10-04 08:41:53 +02:00
Eddie Hung 045f344038 Use `sat -tempinduct` and comments for why equiv_opt not sufficient 2019-10-03 11:11:50 -07:00
Eddie Hung bd5889640b Disable equiv check for ice40 latches 2019-10-03 10:45:53 -07:00
Eddie Hung 5d680590d6 Use equiv_opt -async2sync for xilinx 2019-10-03 10:30:33 -07:00
Clifford Wolf 0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select 
Add -select option to aigmap
 2019-10-03 11:54:04 +02:00
David Shah 9b9d24f15b sv: Improve tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00
David Shah abc155715d sv: Add test scripts for typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah af25585170 sv: Add support for memories of a typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah 30d2326030 sv: Add support for memory typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah e70e4afb60 sv: Fix typedefs in packages 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah c962951612 sv: Fix typedef parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
Eddie Hung e9645c7fa7 Fix broken CI, check reset even for constants, trim rstmux 2019-10-02 21:26:26 -07:00
Eddie Hung e4bd5aaebf Fix test 2019-10-02 18:12:25 -07:00
Eddie Hung c6a55d948a Merge branch 'eddie/fix_sat_init' into eddie/fix1427 2019-10-02 18:07:38 -07:00
Eddie Hung f6fabc8fda Update test 2019-10-02 18:03:45 -07:00
Eddie Hung e730a595ee Add test 2019-10-02 18:01:41 -07:00
Eddie Hung c28d4b8047 Add test that is expecting to fail 2019-10-02 14:52:40 -07:00
Eddie Hung a4f2f7d23c Extend test with renaming cells with prefix too 2019-10-02 12:43:18 -07:00
Sergey eb750670e3
run-test.sh Move $x at end of line. 2019-10-01 11:14:12 +03:00
Sergey e092c4ae6b
Merge branch 'master' into SergeyDegtyar/efinix 2019-10-01 11:04:32 +03:00
Sergey d99b1e3261
Merge branch 'master' into SergeyDegtyar/anlogic 2019-10-01 10:57:09 +03:00
Sergey fc56459746
run-test.sh Move $x at end of line. 2019-10-01 10:55:34 +03:00
Eddie Hung 1caaf51492 equiv_opt with -assert 2019-09-30 19:54:59 -07:00
Eddie Hung f8d5e11aa7 Update resource count for alu.ys 2019-09-30 19:54:04 -07:00
Eddie Hung 369652d4b9 Add test 2019-09-30 17:20:39 -07:00
Eddie Hung 8b239ee707 Add quick test 2019-09-30 15:34:04 -07:00
Eddie Hung d992858318 Move $x to end as per 7f0eec8 2019-09-30 15:15:14 -07:00
Eddie Hung eeb86247c5 Update fsm.ys resource count 2019-09-30 15:14:41 -07:00
Eddie Hung 0bbd1b6364 Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys into eddie/pr1352 2019-09-30 14:57:55 -07:00
whitequark 5c5881695d
Merge pull request #1406 from whitequark/connect_rpc 
rpc: new frontend
 2019-09-30 17:38:20 +00:00
whitequark 99a7f39084 rpc: new frontend. 
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
 2019-09-30 15:53:11 +00:00
Eddie Hung 6216e45eda Add latch test modified from #1363 2019-09-30 12:52:43 +02:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Marcin Kościelnicki fd0e3a2c43 Fix _TECHMAP_REMOVEINIT_ handling. 
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.

Fixes the problem identified in #1396.
 2019-09-27 18:34:12 +02:00
Miodrag Milanovic 7f0eec8270 Change order of parameters, to work on other os 2019-09-27 11:31:55 +02:00
Eddie Hung a009314597
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40 
ICE40 tests. adffs test update (equiv_opt -multiclock).
 2019-09-25 16:43:24 -07:00
SergeyDegtyar b66364ada2 Change sync controls to async. 2019-09-25 14:43:26 +03:00
SergeyDegtyar fc6ebf8268 adffs test update (equiv_opt -multiclock). 2019-09-24 14:55:32 +03:00
Eddie Hung bcee87a457 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-23 10:58:28 -07:00
SergeyDegtyar 1070f2e90b Add new tests for Efinix architecture. 
Problems/questions:
	- fsm.ys. equiv_opt -assert failed because of unproven cells;
	- latches.ys,tribuf.ys - internal cells present;
	- memory.ys - sat called with -verify and proof did fail.
 2019-09-23 15:51:41 +03:00
SergeyDegtyar 27377c4663 Add new tests for Anlogic architecture 
Problems/questions:
	- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
		Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
	- Internal cell type $_TBUF_  is present.
 2019-09-23 12:12:02 +03:00
Eddie Hung 7c8de1dd18 Hell let's add the original #1381 testcase too 2019-09-20 17:58:51 -07:00
Eddie Hung 6258e6a7e2 Add testcase 2019-09-20 17:51:45 -07:00
Eddie Hung 4100825b81 Add more complicated macc testcase 2019-09-19 22:39:15 -07:00
Eddie Hung 2f98f9deee Add mac.sh and macc_tb.v for testing 2019-09-19 18:08:16 -07:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 65fa8adf6c Format macc.v 2019-09-19 11:02:14 -07:00
Marcin Kościelnicki c9f9518de4 Added extractinv pass 2019-09-19 04:02:48 +02:00
Eddie Hung c663a3680b Remove stat 2019-09-18 12:44:34 -07:00
Eddie Hung f7dbfef792 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:40:21 -07:00
Eddie Hung b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext 
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
 2019-09-18 12:40:08 -07:00
Eddie Hung c9fe4d7992 Add .gitignore 2019-09-18 12:11:33 -07:00
Eddie Hung c3cba7ab93 Refine macc testcase 2019-09-18 12:07:25 -07:00
SergeyDegtyar 5eb91fa69f Add comment to dpram test about related issue. 2019-09-18 12:16:04 +03:00
SergeyDegtyar c597c2f2ae adffs test update (equiv_opt -multiclock). div_mod test fix 2019-09-17 12:19:31 +03:00
Eddie Hung f492567c87 Oops 2019-09-13 18:19:07 -07:00
Eddie Hung a2eee9ebef Add counter-example from @cliffordwolf 2019-09-13 16:41:10 -07:00
Eddie Hung 14d72c39c3 Revert "Make one check $shift(x)? only; change testcase to be 8b" 
This reverts commit e2c2d784c8.
 2019-09-13 16:33:18 -07:00
Eddie Hung a1123b095c Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-12 12:11:11 -07:00
David Shah 6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock 
Add equiv_opt -multiclock
 2019-09-12 12:26:28 +01:00
Eddie Hung 7d644f40ed Add AREG=2 BREG=2 test 2019-09-11 17:05:47 -07:00
Eddie Hung c0f26c2da8 Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-11 13:37:11 -07:00
Eddie Hung bdb5e0f29c Cope with presence of reset muxes too 2019-09-11 13:36:37 -07:00
Eddie Hung f46ef47893 Add more tests 2019-09-11 13:22:41 -07:00
Marcin Kościelnicki f72765090c Add -match-init option to dff2dffs. 2019-09-11 19:38:20 +02:00
Eddie Hung 6a95ecd41d Update test with a/b reset 2019-09-11 10:13:13 -07:00
Eddie Hung 36d6db7f8a Extend test for RSTP and RSTM 2019-09-11 09:09:08 -07:00
David Shah c43e52d2d7 Add equiv_opt -multiclock 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-11 13:55:59 +01:00
Eddie Hung fc7008671f Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-11 00:57:25 -07:00
Eddie Hung 3a8582081e proc instead of prep 2019-09-11 00:14:06 -07:00
Eddie Hung 6b23c7c227 Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-11 00:07:33 -07:00
Eddie Hung 580faae8ad Add unsigned case 2019-09-11 00:07:17 -07:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 1fc50a03fc Add SIMD test 2019-09-09 21:40:06 -07:00
Sean Cross 702ce405c1 tests: ice40: fix div_mod SB_LUT4 count 
This test is failing due to one of the changes present in this patchset.
Adjust the test to match the newly-observed values.

https://github.com/xobs/yosys/compare/smtbmc-msvc2-build-fixes...YosysHQ:xobs/pr1362

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-10 08:47:16 +08:00
Marcin Kościelnicki a82e8df7d3 techmap: Add support for extracting init values of ports 2019-09-07 16:30:43 +02:00
Eddie Hung e68507a716 Update macc test 2019-09-06 23:19:03 -07:00
Eddie Hung de8adecd39 Merge branch 'master' of github.com:YosysHQ/yosys 2019-09-06 22:52:00 -07:00
Eddie Hung 173c7936c3 Add missing -assert to equiv_opt 2019-09-06 22:51:44 -07:00
Eddie Hung 97e1520b13 Missing equiv_opt -assert 2019-09-06 22:50:03 -07:00
Eddie Hung e2c2d784c8 Make one check $shift(x)? only; change testcase to be 8b 2019-09-06 22:48:23 -07:00
Eddie Hung 51b559af2c Usee equiv_opt -assert 2019-09-06 22:48:04 -07:00