riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
910 Commits 140 Branches 61 Tags 15 GiB
Commit Graph

108 Commits

Author SHA1 Message Date
Anton Blanchard 562405a302
Fix upstream breakage due to missing docker mount (#80) 2022-04-21 05:34:37 -07:00
Kareem Farid 9ddb806293
gpio_control_block constrains fix (#69) 
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
 2022-04-15 11:50:54 -07:00
R. Timothy Edwards 71600440bc
Caravan top lvs (#67) 
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one

* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
  to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it

* Apply automatic changes to Manifest and README.rst

* add caravan power routing lef

* - update mag and def view of caravan
- add_macro_placement for fake cell

* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines.  Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag.  It may be
worth cherry-picking the files to merge and exclude those layouts.

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
 2022-04-14 15:05:16 -07:00
Jeff DiCorpo b707fbd9b9
Update Makefile (#65) 
fix openlane/Makefile to work around pdk version check
 2022-04-13 12:38:06 -07:00
Jeff DiCorpo 456f49da48
Update Makefile (#62) 2022-04-11 21:18:36 -07:00
Jeff DiCorpo 2957357ce5
avoid pdk version checking in openlane (#61) 
* Update Makefile

Update to workaround pdk version matching in Openlane

* Update Makefile

updated OPENLANE_TAG
 2022-04-11 16:38:49 -07:00
Kareem Farid c84e1393e7
updates to top level caravel (#59) 
* REVERT ME: temporarily match simple_por pin in verilog with lef

* - update configs
- add patch file for power routing def

* - update the following caravel toplevel views
    - gl
    - mag
    - def
- add caravel power routing def

* Apply automatic changes to Manifest and README.rst

* update gl mag and def for caravel

* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c69f.

* update caravel gds

* Apply automatic changes to Manifest and README.rst

* Added text and logo cells back into the caravel top level.  Put an
isolated ground marker layer on the xres_buf layout.  Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v.  Updated the copyright block text.
Corrected DRC errors in the top level routing.

Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
 2022-04-08 09:31:33 -07:00
Kareem Farid dcebeed7e7
Mgmt protect update (#58) 
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect

* mgmt_protect updated

* mgmt_protect updated

* remove some via3 to fix power shorts

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
 2022-04-08 09:29:49 -07:00
Kareem Farid e3b9a99154
- update gpio_control_block config (#57) 
- update gpio_control_block views
- gitignore gds/*gds
 2022-04-08 09:27:51 -07:00
Marwan Abbas e9f023f9fa
Introduction of PDK variable (#39) 
* added PDK_VARIENT variable

* changed variable name to PDK

* resolve issue

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
 2022-04-08 09:05:58 -07:00
kareem 449cb47360 fix comment typo 2022-02-25 10:47:04 -08:00
kareem 0f04a43f58 - change litex tag to mpw-5c 
- warn before deleting when rerunning these targets:
    install_mcw openlane pdk
- clone litex with depth=1 and single branch
- simplified pdk targets by removing these targets:
    skywater-timing build-pdk skywater-library
- add clean-pdk and clean-openlane
- add make prerequisites in pdk (not sure if that's needed)
- run openlane docker non interactive
- export OPENLANE_IMAGE_NAME when running openlane docker
- add check-openlane-env target

Squashed commit of the following:

commit b7904e08ae
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 13:32:36 2022 -0800

    typo

commit 8507bcf1ee
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 11:51:42 2022 -0800

    undo tag for testing

commit 12114e08d2
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 11:50:41 2022 -0800

    typo

commit 1a15d4646a
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 11:47:26 2022 -0800

    fix folder not found check

commit addf24a8b6
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 11:03:31 2022 -0800

    remove export path and ls that were for testing

commit 91a305f365
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 10:57:39 2022 -0800

    typo

commit 00c249db5c
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 10:50:28 2022 -0800

    - use tag for MCW_BRANCH
    - non phony install_mcw
    - clone with depth 1

commit ba14b7a6aa
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 10:39:59 2022 -0800

    the return of non phony

commit f5657bbabf
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 05:04:51 2022 -0800

    revert commit ids of openpdks, magic and openlane (we are going to set them in caravel_user_project)

commit 0fc8c4dacd
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 24 04:46:37 2022 -0800

    gen-source for sky130B

commit c875a7b058
Merge: 801b3dc ff403f5
Author: kareem <kareem.farid@efabless.com>
Date:   Wed Feb 23 14:16:25 2022 -0800

    Merge remote-tracking branch 'upstream/main' into makefile

commit 801b3dc28d
Author: kareem <kareem.farid@efabless.com>
Date:   Wed Feb 23 14:15:25 2022 -0800

    also update openlane, magic, openpdks commit id

commit 47091c6fba
Author: kareem <kareem.farid@efabless.com>
Date:   Tue Feb 22 13:35:07 2022 -0800

    more changes

commit 67a49b0aa2
Author: kareem <kareem.farid@efabless.com>
Date:   Thu Feb 17 11:56:56 2022 -0800

    WIP actual usage of make targets
 2022-02-25 10:39:11 -08:00
Donn 89629b357f Change `make openlane` to `make pull-openlane` in the OpenLane Target 
Merging the image from scratch doesn't work anymore due to a dependency break.

Also, add pdk-with-sram target.
 2022-02-03 18:10:53 +00:00
Jeff DiCorpo e2f00e2770
Merge pull request #14 from Manarabdelaty/doc 
Documentation Updates
 2022-01-18 23:13:26 -08:00
Donn 641096e4ed Move Rectify To Caravel 2022-01-15 23:27:38 +02:00
Manar f6514b37f3
Update openlane.md 2022-01-14 11:27:37 -05:00
manarabdelaty 4773c5c3f8 Merge branch 'doc' of https://github.com/Manarabdelaty/caravel-1 into doc 2022-01-14 10:33:44 -05:00
manarabdelaty c96a65d023 Update doc 2022-01-14 10:33:15 -05:00
Manar a36d0a68fd
Update openlane.md 2022-01-14 10:25:30 -05:00
manarabdelaty 7083c96e34 Add documentation 2022-01-14 10:05:34 -05:00
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
jeffdi 5b1d99f934 Apply automatic changes to Manifest and README.rst 2021-12-17 01:51:53 +00:00
jeffdi e5cf492e0a add documentation 2021-12-16 17:51:16 -08:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
manarabdelaty aa766f9144 [DATA] Update caravel_clocking module 2021-12-05 19:44:28 +02:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
manarabdelaty 8b1c5df909 [DATA] Update caravel_clocking module (timing clean) 2021-11-25 15:23:01 +02:00
manarabdelaty 05278ec738 [DATA] Update HK views (timing clean) 2021-11-25 12:54:22 +02:00
manarabdelaty 83e150bf25 [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
manarabdelaty aeffe4756a [DATA] Add caravan layout 2021-11-22 23:10:25 +02:00
manarabdelaty 38f64d08a3 [DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views 2021-11-22 23:08:25 +02:00
manarabdelaty 1c18c1dae9 [DATA] Update caravel 2021-11-20 17:28:59 +02:00
manarabdelaty 331fdee2bb [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
manarabdelaty 5cd3843f00 [DATA] Update gpio_control_block (li1 used 2um) 2021-11-20 14:43:20 +02:00
manarabdelaty 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
manarabdelaty ededa9ed35 [DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core 2021-11-19 16:51:28 +02:00
manarabdelaty 866755f228 [DATA] Update mgmt_protect mag/gds to remove the shorted power nets 2021-11-19 15:50:36 +02:00
manarabdelaty bf6ad67934 [DATA] Update gpio_control_block pin order to fix shorts at the top level 2021-11-19 13:13:24 +02:00
manarabdelaty 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) 2021-11-19 13:11:18 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
manarabdelaty 61bf3c651e [DATA] Update mgmt_protect pin placement 2021-11-19 01:33:11 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 64bdd6230d [DATA] Update caravel_clocking module floorplan 2021-11-19 01:26:29 +02:00
manarabdelaty 1f55f46596 [DATA] Add chip_io views with the fixed clamped3 pad 2021-11-17 16:42:36 +02:00
manarabdelaty 1b300d7b59 [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
manarabdelaty 46540437af [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 85a1ffc5aa [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 49c506f052 Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency 2021-11-05 18:36:43 +02:00
manarabdelaty e68664101c Update gpio_control_block 2021-11-05 16:54:55 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00