6c925dcded
[regression test] Add more tests for thru channels and deploy to CI
2020-08-19 20:11:37 -06:00
881672d46a
update thru channel arch for avoid buggy pin locations
2020-08-19 19:52:35 -06:00
bf08e1841c
add new test case using thru channels
2020-08-19 17:58:34 -06:00
f0bc6f83f1
disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
2020-08-19 15:34:59 -06:00
18735894f9
bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
2020-08-19 15:27:30 -06:00
3273f441fe
bug fix in the flagship vpr arch
2020-08-19 15:23:20 -06:00
aa4a9b28cc
start testing the initial offset in the flagship architecture
2020-08-19 15:03:46 -06:00
f64079641d
bug fix in flagship vpr arch with frac mem and dsp
2020-08-19 12:43:58 -06:00
d7efdf35b6
add custom pin location to the flagship vpr arch with frac mem and dsp
2020-08-19 11:15:25 -06:00
dbd93e429d
now pro_blif.pl can accept customized clock name
2020-08-19 09:43:44 -06:00
743167521a
add Verilog design for fracturable 32k memory
2020-08-18 21:13:46 -06:00
42b5ea2cb1
bug fix in openfpga arch for frac mem and dsp
2020-08-18 20:42:36 -06:00
3ee4e10aa8
bug fix in the frac mem & DSP vpr arch
2020-08-18 17:25:45 -06:00
098859fe06
bug fix in the frac memory & DSP architecture
2020-08-18 15:05:51 -06:00
21c7eaa9cf
add 36-bit fracturable multiplier Verilog
2020-08-18 14:06:08 -06:00
f833e0ec66
add a flagship architecture using fracturable memory and dsp
2020-08-17 17:49:51 -06:00
1ca2829868
update readme for vpr architecture naming
2020-08-17 13:54:26 -06:00
cadf29022e
add README to explain the organization of regression tests
2020-07-28 13:44:06 -06:00
f33422d4d7
add regression test to track runtime on big fpga devices using practical benchmarks
2020-07-28 12:38:42 -06:00
534c609e17
add fixed layouts to a flagship architecture to test bitstream generation runtime
2020-07-28 11:51:50 -06:00
a156807559
enrich basic regression tests to cover more critical microbenchmarks
2020-07-27 19:47:43 -06:00
5d83abb2cf
bug fix in read architecture bitstream and regression tests
2020-07-27 19:37:05 -06:00
31e7a753a6
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-07-27 19:22:16 -06:00
747c062f86
BugFix : Flow script accepts extra OpenFPGA arguments
2020-07-27 18:10:43 -06:00
50cc4dfba3
classify regression test to dedicated categories
2020-07-27 17:18:59 -06:00
5595ee9052
refine the test case for load external arch bitstream
2020-07-27 16:53:29 -06:00
cec6bf0b6f
add or2 microbenchmark for testing external arch bitstream
2020-07-27 15:59:03 -06:00
4174fbf77d
add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
2020-07-27 15:54:46 -06:00
a3eba8acbe
update task files using the new syntax on SHELL variables
2020-07-27 15:25:49 -06:00
615b557dc4
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-07-27 14:48:23 -06:00
dc7012d590
update regression tests for split fabric_bitstream commands
2020-07-27 14:24:48 -06:00
45af056304
TASK_NAME and TASK_DIR variables are avaialble in config file now
2020-07-27 14:14:57 -06:00
0e46e0d857
Updated task.conf format to have transparent shell variables
2020-07-27 14:08:58 -06:00
177de90822
bug fix in example scripts
2020-07-26 22:10:04 -06:00
f687774452
bug fix in template scripts
2020-07-26 21:46:03 -06:00
41a76126b9
add fabric bitstream writer to CI
2020-07-26 21:44:42 -06:00
c87f6b75b9
add test case for FPGA-SPICE
2020-07-24 19:12:35 -06:00
020154b0cd
add depopulate crossbar test case
2020-07-24 18:06:02 -06:00
021fedbc12
update fabric key to synchronize with new module/instance naming
2020-07-24 12:55:40 -06:00
fefcd88f14
update openfpga architecture README for power-gating
2020-07-22 21:55:59 -06:00
22159531c5
bug fix in power gating support of FPGA-Verilog
2020-07-22 20:21:38 -06:00
ca867ea6fa
add power gate inverter test case (full testbench)
2020-07-22 20:09:52 -06:00
87ef7f9f99
add power gate example architecture
2020-07-22 20:06:10 -06:00
8ade40713a
add missing architecture for CI
2020-07-22 14:07:39 -06:00
1a1c3885e7
use k6 n10 in mux designs to speed up CI
2020-07-22 13:54:09 -06:00
95c1fe61e1
use k6 n8 in mux design to speed up CI
2020-07-22 13:49:03 -06:00
f754c8af06
use k6_n10 architecture to reduce CI runtime
2020-07-22 13:45:55 -06:00
92c3449999
bug fix in the regression test due to benchmark changes
2020-07-22 13:17:05 -06:00
05dccadf21
bug fix in the testcases using yosys_vpr flow
2020-07-22 12:44:19 -06:00
7d39e136a4
enrich micro benchmarks
2020-07-22 12:33:52 -06:00
1d36de817f
adapt generate bitstream testcase to use yosys vpr flow
2020-07-22 12:24:34 -06:00
b96cdbf857
adapt preconfig test cases to use yosys_vpr flow
2020-07-22 12:23:39 -06:00
d8804f4ec1
deploy yosys_vpr flow to basic regression tests
2020-07-22 12:21:59 -06:00
f4e77e3bad
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-07-22 12:09:34 -06:00
3b6cd885f3
BugFix: Fixed yosys_vpr with openFPGA_Shell
2020-07-22 11:57:04 -06:00
eb070694b5
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
2020-07-15 17:52:41 -06:00
ca90f337a7
add fast configuration chain test case
2020-07-15 11:56:47 -06:00
66a50742fc
use configuration chain in the k4k4 test case to speed up CI
2020-07-15 11:56:11 -06:00
1c5bede282
update arch file with device technology binding information
2020-07-13 19:06:51 -06:00
824b56f14c
fabric key can now accept instance name only; decoders are no longer part of the key
2020-07-06 16:42:33 -06:00
1e6955aaa4
rename arch directory to be clear for its usage
2020-07-04 19:13:28 -06:00
f9a2bb0490
Reorganize task directory
2020-07-04 19:06:41 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
1c634e4600
add missing task file for generate bitstream test case
2020-07-02 17:24:51 -06:00
adea6fcec4
add bitstream generation only test case to CI
2020-07-02 16:31:22 -06:00
73e75bf456
add readme for OpenFPGA architecture naming
2020-07-01 10:27:21 -06:00
20cf4acda0
add readme for architecture file naming
2020-07-01 09:54:13 -06:00
b2fb5f760c
update sample key
2020-06-27 15:01:12 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
3d56cd3060
fine tuning on the script for MCNC benchmarks
2020-06-15 20:09:46 -06:00
0d81f60fd8
add new options to openfpga task configuration files
2020-06-12 19:48:39 -06:00
559564c333
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2020-06-12 17:31:14 -06:00
41585436c8
Added external_fabric_key_file key
2020-06-12 15:37:12 -06:00
2d35848cfa
add external key test cases
2020-06-12 13:11:21 -06:00
65b387a589
develop test cases for fabric keys
2020-06-12 11:32:52 -06:00
cf9c3b0f44
add write fabric to test cases
2020-06-12 10:50:23 -06:00
60dd37e086
remove simulation settings from openfpga arch XML
...
update travis to split CI tests
fix errors in travis configuration
fixing travis errors in scripts
keep fixing travis
fix travis on build.sh
bug fixing in travis CI
bug fix in travis regression test run
fixing bugs in the travis scripts
bug fix in travis script: remove common.sh in regression test call
keep bug fixing in travis
2020-06-11 19:31:17 -06:00
068d9943e7
update all the templates and regression test cases with simulation settings
2020-06-11 19:31:16 -06:00
1842bf51e1
deploy read_openfpga_simulation_setting in CI on a single test case
2020-06-11 19:31:16 -06:00
cb09896f23
add example simulation setting for openfpga flow
2020-06-11 19:31:15 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
c87dbc4880
start using counter benchmark in regression tests
2020-06-11 19:31:15 -06:00
f73dfa2bcc
bug fixed in k6_n10_40 architecture
2020-06-11 19:31:15 -06:00
baa2c6b7ef
update arch to support reset signal for SRAm
2020-06-11 19:31:14 -06:00
aac2e8c805
update openfpga architecture for memory bank usage
2020-06-11 19:31:14 -06:00
82b04ae3f0
add SRAM verilog for memory bank usage
2020-06-11 19:31:14 -06:00
3f9afea3e8
add preconfig testbench test case for memory bank configuration protocol
2020-06-11 19:31:14 -06:00
288294c23a
add fast configuration test case for memory bank configuration protocol
2020-06-11 19:31:14 -06:00
73d4c835b7
add regression test case for memory bank
2020-06-11 19:31:13 -06:00
a1ec6833c2
add memory bank example arch xml
2020-06-11 19:31:13 -06:00
2def059b5b
add standalone configuration protocol to pre config test cases
2020-06-11 19:31:12 -06:00
5f6a790eff
add new test cases for the standalone memory configuration protocol
2020-06-11 19:31:12 -06:00
8b5b221a21
add new architecture for standalone memory organization
2020-06-11 19:31:12 -06:00
a5138113e4
add fast configuration testcase
2020-06-11 19:31:12 -06:00
8b3e79766c
add fast configuration option to fpga_verilog to speed up full testbench simulation
2020-06-11 19:31:12 -06:00
05aa166a9e
add preconfig testbench cases to regression tests for different configuration protocols
2020-06-11 19:31:11 -06:00
827e2e6713
file moving in regression tests
2020-06-11 19:31:11 -06:00
b5e5182f52
frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
2020-06-11 19:31:11 -06:00
583c15131b
change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog
2020-06-11 19:31:11 -06:00
6a72c66eb8
bug fixed for frame-based configuration memory in top-level full testbench
2020-06-11 19:31:11 -06:00
tangxifan
ganeshgore