ganeshgore
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1554f583b7
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[Flow] Now support explicit variable file for task
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2020-11-25 17:22:41 -07:00 |
tangxifan
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7729f671ab
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[Regression Tests] Remove deadlink
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2020-09-22 18:35:41 -06:00 |
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tangxifan
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51c0319657
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[Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:32:54 -06:00 |
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tangxifan
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70b8b02f74
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[Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:32:11 -06:00 |
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tangxifan
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72749be4bd
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[Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:31:34 -06:00 |
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tangxifan
|
61bcbaafd8
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[Architecture] Add Verilog HDL for fracturable 32-bit multiplier
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2020-09-22 15:15:19 -06:00 |
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tangxifan
|
3d1f49fb2f
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[Regression Test] Add testcase for k4n4 with multiple segments
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2020-09-22 12:47:41 -06:00 |
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tangxifan
|
13df6c1c21
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[Architecture] Add openfpga architecture for k4n4 using multiple segments
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2020-09-22 12:36:11 -06:00 |
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tangxifan
|
8a3934b749
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[Architecture Add vpr architecture for k4n4 using multiple wire segments
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2020-09-22 12:35:39 -06:00 |
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tangxifan
|
5741664580
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[Regression Test] Add test case for k4n4 bram architecture
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2020-09-22 12:23:56 -06:00 |
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tangxifan
|
ddf999b6b9
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[Architecture] Add verilog HDL for dual-port BRAM 1k
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2020-09-22 12:23:28 -06:00 |
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tangxifan
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26fba4a94b
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[Architecture] Add openfpga architectue for k4n4 with bram blocks
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2020-09-22 12:22:59 -06:00 |
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tangxifan
|
daf776b7b1
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[Architecture] Add k4n4 architecture with bram block for basic tests
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2020-09-22 12:22:32 -06:00 |
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tangxifan
|
3bf94b8e34
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[Regression test] Remove no local routing from fpga verilog tests
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2020-09-22 11:48:19 -06:00 |
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tangxifan
|
7ed9f76b06
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[Regression test] Move k4n4 no local routing to basic test
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2020-09-22 11:47:03 -06:00 |
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tangxifan
|
2dea97afb6
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[Regression test] reduce runtime for k4n4 test in basic testing
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2020-09-22 11:45:29 -06:00 |
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tangxifan
|
ea4dd410b7
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[Regression Test] Add k4n4 fracturable lut test case to basic test
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2020-09-22 11:41:36 -06:00 |
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tangxifan
|
dad19cac9a
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[Regression test] Add k4 series architecture: fracturable adder
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2020-09-22 11:39:18 -06:00 |
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tangxifan
|
dd192a2f54
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[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
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2020-09-22 11:34:23 -06:00 |
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tangxifan
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7a6f5a06f7
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[Architecture] Add a k4n4 architecture with carry chain to quick test
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2020-09-22 11:33:56 -06:00 |
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tangxifan
|
aa5f5fc7e0
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[Architecture] Bring back pin equivalence for no local routing architecture
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2020-09-21 22:22:39 -06:00 |
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tangxifan
|
a8a269aa82
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[Architecture] Temporary patch for the no local routing architecture
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2020-09-21 19:51:23 -06:00 |
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tangxifan
|
acf318f184
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[Regression test] Bug fix in test case fabric_chain
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2020-09-21 18:58:35 -06:00 |
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tangxifan
|
e4291eb27e
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[Regression Tests] Now use fixed device layout in test cases for best coverage
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2020-09-21 18:44:13 -06:00 |
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tangxifan
|
7a57cc9cf4
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[Architecture] A new device layout to k4n4 to test untileable architecture
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2020-09-21 18:36:50 -06:00 |
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tangxifan
|
2bbfcb5753
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[Architecture] Add a new device layout to k4n4 for testing tileable routing
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2020-09-21 18:34:31 -06:00 |
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tangxifan
|
e1c5947143
|
[Architecture] Add auto layout and fixed layout to architectures
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2020-09-21 18:01:51 -06:00 |
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tangxifan
|
936a164eee
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[OpenFPGA flow] Add a new template script to use a fixed device layout
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2020-09-21 17:48:28 -06:00 |
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tangxifan
|
d7f8b3abad
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[Architecture] Add k4 N4 untilable architecture
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2020-09-21 17:44:37 -06:00 |
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tangxifan
|
a83bc3f75c
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[Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI
|
2020-09-21 17:38:16 -06:00 |
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tangxifan
|
e9c0e90544
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[Architecture] Add a VPR architectue using fracturable LUT4
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2020-09-21 17:37:26 -06:00 |
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tangxifan
|
60f328a2ab
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[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
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2020-09-21 17:36:57 -06:00 |
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tangxifan
|
681e80d4b6
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[Regression tests] update frac_lut test case using more representative benchmarks
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2020-09-17 10:39:22 -06:00 |
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tangxifan
|
367cf59efd
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[Benchmark] Bug fix in the and2_or2 benchmark
|
2020-09-17 10:35:13 -06:00 |
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tangxifan
|
de48b8c7b2
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[Benchmark] Add a new micro benchmark to test fracturable LUTs
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2020-09-17 10:21:25 -06:00 |
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tangxifan
|
ca1bafc688
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[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture
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2020-09-16 19:26:12 -06:00 |
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tangxifan
|
c22d8e2421
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[Architecture] Bug fix in no local routing architecture
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2020-09-16 18:07:52 -06:00 |
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tangxifan
|
c40c9f5876
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[Regression test] add test case for no local routing architecture
|
2020-09-16 18:05:33 -06:00 |
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tangxifan
|
f5b7ac6269
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[OpenFPGA Architecture] Add a new architecture with no local routing
|
2020-09-16 18:04:55 -06:00 |
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tangxifan
|
35d47ee0e7
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[Regression tests] bug fix in the test case for fully connected output crossbar
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2020-09-16 17:33:54 -06:00 |
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tangxifan
|
030d7f02f8
|
[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
|
2020-09-16 17:30:08 -06:00 |
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tangxifan
|
30fb99095f
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[Regression Tests] Add new test case for fully connected output crossbar
|
2020-09-16 17:29:15 -06:00 |
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tangxifan
|
3c0faf0021
|
[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
|
2020-09-16 17:27:24 -06:00 |
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tangxifan
|
f42411c29e
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[Regression Tests] Add test cases for routing multiplexer design with input/output buffers only
|
2020-09-14 16:03:43 -06:00 |
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tangxifan
|
aaf63050bb
|
[OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers
|
2020-09-14 15:58:34 -06:00 |
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tangxifan
|
aa9521b23b
|
[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
|
2020-09-14 15:57:44 -06:00 |
|
tangxifan
|
eecfd186f0
|
[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
|
2020-09-14 15:46:10 -06:00 |
|
tangxifan
|
9bf0e772a3
|
[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
|
2020-09-14 15:45:35 -06:00 |
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tangxifan
|
4b3142c4ee
|
[Architecture File] Patch openfpga architecture with default circuit model definition
|
2020-08-23 15:13:28 -06:00 |
|
tangxifan
|
9101ba1021
|
[Architecture Language] Update openfpga architecture files for default models
|
2020-08-23 14:55:44 -06:00 |