tangxifan
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ca3617a029
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[core] code format
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2023-09-20 20:37:27 -07:00 |
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tangxifan
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1ef38b6a64
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[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
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2023-09-20 20:34:21 -07:00 |
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tangxifan
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c105b56bf0
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[core] code format
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2023-09-18 23:31:27 -07:00 |
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tangxifan
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43fd08a3fe
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[core] fixed a bug
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2023-09-18 23:31:09 -07:00 |
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tangxifan
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4d11f73471
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[core] fixed a bug
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2023-09-18 20:43:15 -07:00 |
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tangxifan
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a1e609c901
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[core] fixed some bugs
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2023-09-18 16:39:07 -07:00 |
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tangxifan
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1daabb990e
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[core] code format
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2023-09-18 15:35:13 -07:00 |
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tangxifan
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110301a2e4
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[core] now tile port naming can follow index
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2023-09-18 15:34:40 -07:00 |
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tangxifan
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e46e58527a
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[core] code format
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2023-09-17 23:16:38 -07:00 |
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tangxifan
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eeb1bd6662
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[core] fixed some bugs
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2023-09-17 23:16:15 -07:00 |
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tangxifan
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c6175aa514
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[core] code format
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2023-09-17 22:37:48 -07:00 |
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tangxifan
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ef97127c63
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[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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tangxifan
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c14277a674
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[core] fixing bugs
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2023-09-17 17:57:57 -07:00 |
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tangxifan
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d5152dc16d
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[core] fixed a bug on the hierarchy writer
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2023-09-17 17:42:25 -07:00 |
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tangxifan
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4ccb4737be
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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tangxifan
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f79da76656
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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tangxifan
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72a3c05747
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[core] code format
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2023-09-17 13:29:30 -07:00 |
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tangxifan
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ccd4c1861b
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[core] developing new command to write module naming rules
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2023-09-16 19:37:06 -07:00 |
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tangxifan
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32df673d72
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[core] code format
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2023-09-16 18:35:33 -07:00 |
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tangxifan
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200ecad74a
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[core] fixed bugs in bitgen
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2023-09-16 18:34:55 -07:00 |
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tangxifan
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058bb1ef51
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[core] code format
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2023-09-16 18:24:38 -07:00 |
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tangxifan
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6fc2924438
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[core] syntax
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2023-09-16 18:16:30 -07:00 |
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tangxifan
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d61d88f12e
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[core] fixed some bugs in verilog writer due to renaming
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2023-09-16 18:13:22 -07:00 |
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tangxifan
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37573abc22
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[core] code format
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2023-09-15 23:32:40 -07:00 |
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tangxifan
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c85c64eb5a
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[core] syntax
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2023-09-15 23:30:34 -07:00 |
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tangxifan
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bc407e5d69
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[core] code complete for rename modules
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2023-09-15 23:22:31 -07:00 |
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tangxifan
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2a45b49890
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[core] developing renaming commands. options and functions
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2023-09-15 19:15:18 -07:00 |
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tangxifan
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af67b02cca
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[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
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2023-09-15 13:51:14 -07:00 |
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tangxifan
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eaadff3448
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[core] fixed some bugs
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2023-09-06 22:49:56 -07:00 |
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tangxifan
|
bcb82d43af
|
[core] code format
|
2023-09-06 22:40:59 -07:00 |
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tangxifan
|
2fee56548b
|
[core] fixed some bugs
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2023-09-06 22:39:59 -07:00 |
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tangxifan
|
f544953085
|
[core] code format
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2023-09-06 22:29:30 -07:00 |
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tangxifan
|
f8b2eec988
|
[core] now default net type wire will not appear. timescale does not show in fabric netlists
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2023-09-06 22:27:51 -07:00 |
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tangxifan
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539bcba851
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[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
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2023-09-06 17:23:41 -07:00 |
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tangxifan
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dfe5447e2a
|
[core] format
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2023-08-25 15:21:24 -07:00 |
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tangxifan
|
b8c66b06a0
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[core] syntax
|
2023-08-25 15:17:52 -07:00 |
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tangxifan
|
717906ea17
|
[core] code format
|
2023-08-25 15:13:39 -07:00 |
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tangxifan
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89b392a51f
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[core] adapt changes in is_sb_exist()
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2023-08-25 15:13:00 -07:00 |
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tangxifan
|
55e5f738ce
|
[core] code format
|
2023-08-25 11:58:15 -07:00 |
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tangxifan
|
92f92658c9
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[core] remove useless errors
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2023-08-25 11:53:49 -07:00 |
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tangxifan
|
a6d43beaca
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[core] now tile verilog writer supports relative paths
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2023-08-21 22:25:52 -07:00 |
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tangxifan
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66cc375996
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[core] remove debugging messages
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2023-08-18 22:08:47 -07:00 |
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tangxifan
|
19d4d9a16d
|
[core] code format
|
2023-08-18 21:05:26 -07:00 |
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tangxifan
|
fc523bed32
|
[core] fixed some bugs in spotting the correct pin index of given subtiles
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2023-08-18 21:04:37 -07:00 |
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tangxifan
|
3d8f76269a
|
[core] fixed a bug when io is in the center of 3x3 fabric
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2023-08-18 12:42:15 -07:00 |
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tangxifan
|
e9fd22790d
|
[core] fixed a bug where pass thru cb blocks are not connected in tiles
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2023-08-17 15:26:32 -07:00 |
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tangxifan
|
399f087c50
|
[core] code format
|
2023-08-17 13:54:31 -07:00 |
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tangxifan
|
414f7379c6
|
[core] fixed some bugs in debugging messages
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2023-08-17 13:52:21 -07:00 |
chungshien
|
aabbd330b3
|
Address follow up from PR 1259 (1)
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2023-08-11 08:06:57 -07:00 |
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chungshien
|
6c0df8da20
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Address follow up from PR 1259
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2023-08-11 07:59:53 -07:00 |