Andrew Zonenberg
|
134e093e4e
|
Added GP_PGA cell
|
2016-04-27 23:07:21 -07:00 |
Andrew Zonenberg
|
d57c85111f
|
Merge https://github.com/cliffordwolf/yosys
|
2016-04-24 22:11:56 -07:00 |
Andrew Zonenberg
|
349d717202
|
Removed VIN_BUF_EN
|
2016-04-24 17:01:21 -07:00 |
Andrew Zonenberg
|
6e215f374d
|
Renamed VOUT to OUT on GP_ACMP cell
|
2016-04-23 22:53:49 -07:00 |
Andrew Zonenberg
|
512486dcf3
|
Added GP_ACMP cell
|
2016-04-23 22:33:36 -07:00 |
Clifford Wolf
|
09ffebb995
|
Added "prep -flatten" and "synth -flatten"
|
2016-04-24 00:48:33 +02:00 |
Clifford Wolf
|
77aa2031e7
|
Converted "prep" to ScriptPass
|
2016-04-24 00:48:06 +02:00 |
Clifford Wolf
|
c9c5192cd6
|
Run clean after splitnets in synth_greenpak4
|
2016-04-23 23:09:45 +02:00 |
Clifford Wolf
|
34195f281f
|
Merge https://github.com/azonenberg/yosys
|
2016-04-23 10:33:32 +02:00 |
Clifford Wolf
|
f85cfa5666
|
Added "shregmap" to synth_greenpak4
|
2016-04-23 10:31:19 +02:00 |
Clifford Wolf
|
a24021ea20
|
Converted synth_greenpak4 to ScriptPass
|
2016-04-23 10:27:33 +02:00 |
Andrew Zonenberg
|
0cbe70eaa4
|
Fixed typo
|
2016-04-22 19:08:19 -07:00 |
Andrew Zonenberg
|
ab11f2aa70
|
Merge https://github.com/cliffordwolf/yosys
|
2016-04-22 19:07:55 -07:00 |
Clifford Wolf
|
0bc95f1e04
|
Added "yosys -D" feature
|
2016-04-21 23:28:37 +02:00 |
Andrew Zonenberg
|
d90c1e9522
|
Added GP_VREF cell
|
2016-04-20 20:48:19 -07:00 |
Andrew Zonenberg
|
d0aaf8d262
|
Added GP_SHREG cell
|
2016-04-13 23:13:51 -07:00 |
Andrew Zonenberg
|
cdefa60367
|
Refactoring: alphabetized cells_sim
|
2016-04-13 23:13:39 -07:00 |
Andrew Zonenberg
|
f1679936fe
|
Fixed missing semicolon
|
2016-04-09 01:18:02 -07:00 |
Andrew Zonenberg
|
58d8715681
|
Added GP_RCOSC cell
|
2016-04-09 01:17:13 -07:00 |
Andrew Zonenberg
|
01a5f71187
|
Fixed assertion failure for non-inferrable counters in some cases
|
2016-04-06 23:42:22 -07:00 |
Andrew Zonenberg
|
48c10d90f4
|
Added second divider to GP_RINGOSC
|
2016-04-06 23:10:34 -07:00 |
Andrew Zonenberg
|
1df559c706
|
Added GP_RINGOSC primitive
|
2016-04-06 22:40:25 -07:00 |
Andrew Zonenberg
|
c2b909c051
|
Added GP_POR
|
2016-04-04 21:46:07 -07:00 |
Andrew Zonenberg
|
c01ff05fab
|
Added GP_BANDGAP cell
|
2016-04-04 16:56:43 -07:00 |
Andrew Zonenberg
|
34667ded53
|
Removed more debug prints
|
2016-04-01 23:41:03 -07:00 |
Andrew Zonenberg
|
87e7cd9fbd
|
Removed forgotten debug code
|
2016-04-01 23:39:32 -07:00 |
Andrew Zonenberg
|
2386885f22
|
Added GreenPak inverter support
|
2016-04-01 21:18:29 -07:00 |
Andrew Zonenberg
|
6dbcf50fa1
|
Added support for inferring counters with asynchronous resets. Fixed use-after-free in inference pass.
|
2016-04-01 18:07:59 -07:00 |
Andrew Zonenberg
|
f277267916
|
Merge https://github.com/cliffordwolf/yosys
|
2016-04-01 00:03:00 -07:00 |
Andrew Zonenberg
|
736a998a75
|
DFFINIT is now correctly called for all kinds of flipflop, not just DFF
|
2016-03-31 23:16:45 -07:00 |
Andrew Zonenberg
|
7498ff8041
|
Fixed incorrect port name in cells_map.v
|
2016-03-31 22:51:22 -07:00 |
Clifford Wolf
|
2553319081
|
Added ScriptPass helper class for script-like passes
|
2016-03-31 11:16:34 +02:00 |
Andrew Zonenberg
|
c04a3d2763
|
Fixed typo (wasn't written in 2012)
|
2016-03-30 23:58:45 -07:00 |
Clifford Wolf
|
ec93680bd5
|
Renamed opt_share to opt_merge
|
2016-03-31 08:52:49 +02:00 |
Clifford Wolf
|
1d0f0d668a
|
Renamed opt_const to opt_expr
|
2016-03-31 08:46:56 +02:00 |
Clifford Wolf
|
d31c968d76
|
Fixed typo in greenpak4_counters.cc
|
2016-03-31 08:00:59 +02:00 |
Andrew Zonenberg
|
984561c034
|
Renamed counters pass to greenpak4_counters
|
2016-03-30 22:52:01 -07:00 |
Andrew Zonenberg
|
1ae33344f4
|
Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now.
|
2016-03-30 22:40:14 -07:00 |
Andrew Zonenberg
|
94a6923e7d
|
Updated tech lib for greenpak4 counter with some clarifications
|
2016-03-30 20:30:25 -07:00 |
Andrew Zonenberg
|
489caf32c5
|
Initial work on greenpak4 counter extraction. Doesn't work but a decent start
|
2016-03-30 01:07:20 -07:00 |
Andrew Zonenberg
|
3ea6026648
|
Added splitnets to synth_greenpak4
|
2016-03-29 20:02:59 -07:00 |
Clifford Wolf
|
19c20235b5
|
Added more cell help messages
|
2016-03-29 15:14:43 +02:00 |
Clifford Wolf
|
8c8b2e72b1
|
Fixed indenting in techlibs/greenpak4/gp_dff.lib
|
2016-03-29 13:44:14 +02:00 |
Andrew Zonenberg
|
75f0030458
|
Added keep constraint to GP_SYSRESET cell
|
2016-03-28 23:16:43 -07:00 |
Andrew Zonenberg
|
ea9cc03092
|
Added GP_SYSRESET block
|
2016-03-28 22:49:46 -07:00 |
Andrew Zonenberg
|
3197b6c372
|
Added GP_COUNT8/GP_COUNT14 cells
|
2016-03-26 23:29:02 -07:00 |
Andrew Zonenberg
|
31a7567aff
|
Changed GP_LFOSC parameter configuration
|
2016-03-26 14:13:52 -07:00 |
Andrew Zonenberg
|
44fd3cd149
|
Added GP_LFOSC cell
|
2016-03-26 13:42:53 -07:00 |
Andrew Zonenberg
|
af15b92c86
|
Renamed GP4_V* cells to GP_V* for consistency
|
2016-03-26 13:42:41 -07:00 |
Clifford Wolf
|
b4bf787f10
|
Added GP_DFFS, GP_DFFR, and GP_DFFSR
|
2016-03-23 08:46:10 +01:00 |
Clifford Wolf
|
456c10f16e
|
Added GP_DFF INIT parameter
|
2016-03-23 08:12:54 +01:00 |
Clifford Wolf
|
ca8f8e30f2
|
Improvements in synth_greenpak4, added -part option
|
2016-03-21 09:44:52 +01:00 |
Clifford Wolf
|
ff5c61b120
|
Added black box modules for all the 7-series design elements (as listed in ug953)
|
2016-03-19 11:09:10 +01:00 |
Clifford Wolf
|
a75f94ec4a
|
Run dffsr2dff in synth_xilinx
|
2016-02-13 08:20:19 +01:00 |
Clifford Wolf
|
0ccfb88728
|
Work around DDR dout sim glitches in ice40 SB_IO sim model
|
2016-02-07 11:19:48 +01:00 |
Clifford Wolf
|
d69395ca08
|
Added dffsr2dff
|
2016-02-02 17:19:01 +01:00 |
Clifford Wolf
|
bd10927f45
|
Progress in cell library documentation
|
2016-02-01 13:58:10 +01:00 |
Clifford Wolf
|
17372d8abd
|
Added "abc -luts" option, Improved Xilinx logic mapping
|
2016-02-01 12:40:32 +01:00 |
Clifford Wolf
|
2ee608246f
|
Re-run ice40_opt in "synth_ice40 -abc2"
|
2015-12-22 12:19:11 +01:00 |
Clifford Wolf
|
3102ffbb83
|
Improvements in ice40_opt
|
2015-12-22 12:18:38 +01:00 |
Clifford Wolf
|
8bf452c364
|
Bugfix in ice40_ffinit
|
2015-12-22 12:18:06 +01:00 |
Clifford Wolf
|
ec93d258a4
|
Improved ice40_ffinit
|
2015-12-22 11:15:25 +01:00 |
Clifford Wolf
|
f1b959dc69
|
Run opt_const before check in default scripts
|
2015-12-22 11:15:05 +01:00 |
Clifford Wolf
|
494e5f24f9
|
Added "synth_ice40 -abc2"
|
2015-12-08 11:16:26 +01:00 |
Clifford Wolf
|
4d0a6dac7b
|
Merge pull request #108 from cseed/master
Added LO to ICESTORM_LC for LUT cascade route.
|
2015-12-07 03:32:20 +01:00 |
Cotton Seed
|
9f5b6e4cbc
|
Added LO to ICESTORM_LC for LUT cascade route.
|
2015-12-06 17:24:48 -05:00 |
Clifford Wolf
|
0793f1b196
|
Added ice40_ffinit pass
|
2015-11-26 18:11:06 +01:00 |
Clifford Wolf
|
8ff229a3ea
|
Fixed WE/RE usage in iCE40 BRAM mapping
|
2015-11-24 10:51:34 +01:00 |
Clifford Wolf
|
3ad742056b
|
Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling
|
2015-11-06 17:02:16 +01:00 |
Clifford Wolf
|
864808992b
|
Bugfix in Xilinx LUT mapping
|
2015-10-30 13:58:03 +01:00 |
Clifford Wolf
|
bbcbf739e6
|
Progress on cell help messages
|
2015-10-20 16:49:11 +02:00 |
Clifford Wolf
|
5d1c0ce7c0
|
Progress on cell help messages
|
2015-10-17 02:35:19 +02:00 |
Clifford Wolf
|
25c1f6e605
|
Added "prep" command
|
2015-10-14 22:46:41 +02:00 |
Clifford Wolf
|
87adb523aa
|
Added more cell descriptions
|
2015-10-14 20:30:59 +02:00 |
Clifford Wolf
|
7d3a3a3173
|
Added first help messages for cell types
|
2015-10-14 16:27:42 +02:00 |
Clifford Wolf
|
f42218682d
|
Added examples/ top-level directory
|
2015-10-13 15:41:20 +02:00 |
Clifford Wolf
|
924d9d6e86
|
Added read-enable to memory model
|
2015-09-25 12:23:11 +02:00 |
Clifford Wolf
|
598a475724
|
Added nlutmap
|
2015-09-18 21:57:34 +02:00 |
Clifford Wolf
|
745d56149d
|
Renamed GreenPAK4 cells, improved GP4 DFF mapping
|
2015-09-18 12:00:37 +02:00 |
Clifford Wolf
|
d9cecabb87
|
Fixed copy&paste typo in synth_greenpak4
|
2015-09-16 09:39:31 +02:00 |
Clifford Wolf
|
c5352f45c3
|
Added GreenPAK4 skeleton
|
2015-09-16 09:28:37 +02:00 |
Clifford Wolf
|
99ccb3180d
|
Fixed ice40 handling of negclk RAM40
|
2015-09-10 17:35:19 +02:00 |
Clifford Wolf
|
c475deec6c
|
Switched to Python 3
|
2015-08-22 09:59:33 +02:00 |
Clifford Wolf
|
9596fe74de
|
Another bugfix for ice40 and xilinx brams_init make rules
|
2015-08-16 21:39:34 +02:00 |
Clifford Wolf
|
aedcfd6fd3
|
Fixed Makefile rules for generated share files
|
2015-08-16 21:15:07 +02:00 |
Clifford Wolf
|
d5b1a90b33
|
Added $tribuf and $_TBUF_ sim models
|
2015-08-16 13:05:32 +02:00 |
Clifford Wolf
|
9c33172ece
|
Added tribuf command
|
2015-08-16 12:55:25 +02:00 |
Clifford Wolf
|
ff50bc2ac3
|
Added $tribuf and $_TBUF_ cell types
|
2015-08-16 12:54:52 +02:00 |
Larry Doolittle
|
6c00704a5e
|
Another block of spelling fixes
Smaller this time
|
2015-08-14 23:27:05 +02:00 |
Clifford Wolf
|
e4ef000b70
|
Adjust makefiles to work with out-of-tree builds
This is based on work done by Larry Doolittle
|
2015-08-12 15:04:44 +02:00 |
Clifford Wolf
|
c43f38c81b
|
Improved handling of "keep" attributes in hierarchical designs in opt_clean
|
2015-08-12 14:10:14 +02:00 |
Marcus Comstedt
|
c9e56bc428
|
Added iCE40 WARMBOOT cell
|
2015-08-06 22:58:17 +02:00 |
Clifford Wolf
|
8d6d5c30d9
|
Added WORDS parameter to $meminit
|
2015-07-31 10:40:09 +02:00 |
Clifford Wolf
|
516e8828f2
|
Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
|
2015-07-27 22:44:01 +02:00 |
Clifford Wolf
|
c6ca4780e2
|
iCE40 DFF sim models: init Q regs to 0
|
2015-07-20 13:05:18 +02:00 |
Clifford Wolf
|
54588a276a
|
Avoid tristate warning for blackbox ice40/cells_sim.v
|
2015-07-18 11:59:04 +02:00 |
Clifford Wolf
|
85aaf08e53
|
Improved liberty file test case
|
2015-07-06 17:45:56 +02:00 |
Clifford Wolf
|
f0c9a099d2
|
Added "synth -nofsm"
|
2015-07-02 15:25:38 +02:00 |
Clifford Wolf
|
6c84341f22
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
Clifford Wolf
|
df0163cd2b
|
iCE40: set min bram efficiency to 2%
|
2015-06-20 09:31:19 +02:00 |