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991 Commits

Author SHA1 Message Date
Clifford Wolf a0b57f2a6f Cleanup tux3-implicit_named_connection 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 11:46:16 +02:00
Clifford Wolf b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
tux3 88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00
Clifford Wolf b894187cf6
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn 
Added support for parsing attributes on port connections.
 2019-06-06 12:34:05 +02:00
Maciej Kurc 03e0d3a17c Fixed memory leak. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-05 10:42:43 +02:00
Clifford Wolf 36120fcc30 Only support Symbiotic EDA flavored Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-02 10:14:50 +02:00
Maciej Kurc a6cadf6318 Added support for parsing attributes on port connections. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-31 14:58:43 +02:00
Clifford Wolf 2faa1d0e80 Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-30 10:04:26 +02:00
Stefan Biereigel 816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel cd12f2ddcf remove leftovers from ast data structures 2019-05-27 18:01:44 +02:00
Stefan Biereigel ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf 92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range 
Give error instead of asserting for invalid range, fixes #947
 2019-05-27 13:26:12 +02:00
Miodrag Milanovic 84ffb21708 Give error instead of asserting for invalid range, fixes #947 2019-05-27 12:25:18 +02:00
Miodrag Milanovic 34417ce55f Added support for unsized constants, fixes #1022 
Includes work from @sumit0190 and @AaronKel
 2019-05-27 11:42:10 +02:00
Stefan Biereigel 85de9d26c1 fix assignment of non-wires 2019-05-23 17:55:56 +02:00
Stefan Biereigel fd003e0e97 fix indentation across files 2019-05-23 13:57:27 +02:00
Stefan Biereigel 075a48d3fa implementation for assignments working 2019-05-23 13:57:27 +02:00
Stefan Biereigel 9df04d7e75 make lexer/parser aware of wand/wor net types 2019-05-23 13:57:27 +02:00
Eddie Hung 7057753427 Rename label 2019-05-21 18:20:31 -07:00
Eddie Hung b5a29460b9 Try again 2019-05-21 17:20:19 -07:00
Eddie Hung 1bff09f2ff Fix warning 2019-05-21 16:26:20 -07:00
Kaj Tuomi 48ddbe52fb Read bigger Verilog files. 
Hit parser limit with 3M gate design. This commit fix it.
 2019-05-18 14:20:30 +03:00
Clifford Wolf b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes 
Support for attributes on parameters and localparams for Verilog frontend
 2019-05-16 14:21:18 +02:00
Maciej Kurc ce4a0954bc Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:44:16 +02:00
Henner Zeller 8eb2798776 Make the generated *.tab.hh include all the headers needed to define the union. 2019-05-14 21:07:26 -07:00
Clifford Wolf 752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify 
Add specify parser
 2019-05-06 20:57:15 +02:00
Clifford Wolf 1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968 
Re-enable "final loop assignment" feature and fix opt_clean warnings
 2019-05-06 20:53:38 +02:00
Clifford Wolf 7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import 
Improve verific -chparam and add hierarchy -chparam
 2019-05-06 20:51:59 +02:00
Clifford Wolf d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00
Clifford Wolf 20268d12a5 Fix the other bison warning in ilang_parser.y 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 15:38:43 +02:00
Clifford Wolf 1cd1b5fc1a Add "real" keyword to ilang format 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 12:00:40 +02:00
Clifford Wolf c7f2e93024 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify 2019-05-06 11:46:10 +02:00
Ben Widawsky a98069d762 verilog_parser: Fix Bison warning 
As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
 %name-prefix "frontend_verilog_yy"

For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html

Compile tested only.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-05-05 19:36:27 -07:00
Clifford Wolf 70d0f389ad
Merge pull request #988 from YosysHQ/clifford/fix987 
Add approximate support for SV "var" keyword
 2019-05-04 21:58:25 +02:00
Clifford Wolf 66d6ca2de2 Add support for SVA "final" keyword 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 09:25:32 +02:00
Clifford Wolf 87426f5a06 Improve write_verilog specify support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 08:46:24 +02:00
Clifford Wolf 9804c86e87 Add approximate support for SV "var" keyword, fixes #987 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 07:52:51 +02:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Eddie Hung c7d7d8ad1b For hier_tree::Elaborate() also include SV root modules (bind) 2019-05-03 20:53:25 +02:00
Eddie Hung 3ea54ec400 Fix verific_parameters construction, use attribute to mark top netlists 2019-05-03 20:53:25 +02:00
Eddie Hung a27b42e975 WIP -chparam support for hierarchy when verific 2019-05-03 20:53:25 +02:00
Eddie Hung 0f1a4cc03c verific_import() changes to avoid ElaborateAll() 2019-05-03 20:53:25 +02:00
Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Clifford Wolf 6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 10:01:54 +02:00
Clifford Wolf 3b6a02d3a7 Fix width detection of memory access with bit slice, fixes #974 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:57:26 +02:00
Clifford Wolf 59d74a3348 Re-enable "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:02:39 +02:00
Clifford Wolf e35fe1344d Disabled "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 20:22:50 +02:00
Clifford Wolf 9c7d23446d
Merge pull request #972 from YosysHQ/clifford/fix968 
Add final loop variable assignment when unrolling for-loops
 2019-04-30 18:09:44 +02:00
Clifford Wolf 84f3a796e1 Include filename in "Executing Verilog-2005 frontend" message, fixes #959 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:37:46 +02:00
Clifford Wolf 9af825e31e Add final loop variable assignment when unrolling for-loops, fixes #968 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:03:32 +02:00
Clifford Wolf 64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00
Eddie Hung d9c915042a Move clean from aigerparse to abc9 2019-04-23 13:42:35 -07:00
Clifford Wolf 4575e4ad86 Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:18:04 +02:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 012c6af088 Allow $specify[23] cells in blackbox modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf b232e027bf Checking and fixing specify cells in genRTLIL 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 41b843c27b Un-break default specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 3cc95fb4be Add specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Eddie Hung 5f30a8795d Tidy up 2019-04-22 17:47:05 -07:00
Eddie Hung 8f30019b68 Revert "Temporarily remove 'r' extension" 
This reverts commit eaf3c24772.
 2019-04-22 17:41:21 -07:00
Eddie Hung eaf3c24772 Temporarily remove 'r' extension 2019-04-22 11:54:19 -07:00
Eddie Hung 4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Clifford Wolf bc98a463a4
Merge pull request #952 from YosysHQ/clifford/fix370 
Determine correct signedness and expression width in for-loop unrolling
 2019-04-22 20:10:46 +02:00
Clifford Wolf 4ad0ea5c3c Determine correct signedness and expression width in for loop unrolling, fixes #370 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 18:19:02 +02:00
Clifford Wolf e158ea2097 Add log_debug() framework 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 17:25:52 +02:00
Clifford Wolf b40af877f3
Merge pull request #909 from zachjs/master 
support repeat loops with constant repeat counts outside of constant functions
 2019-04-22 08:51:34 +02:00
Eddie Hung 42a6e0b0b9 Merge remote-tracking branch 'origin/clifford/libwb' into xaig 2019-04-21 14:49:18 -07:00
Clifford Wolf 5b7fea5245 Add "noblackbox" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-21 11:40:09 +02:00
Clifford Wolf fb7f02be55 New behavior for front-end handling of whiteboxes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 22:24:50 +02:00
Eddie Hung 21701cc1df read_aiger to parse 'r' extension 2019-04-18 17:39:36 -07:00
Eddie Hung 8fe0a961b3 Merge remote-tracking branch 'origin/clifford/whitebox' into xaig 2019-04-18 09:00:06 -07:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Eddie Hung e1b550d203 Ignore a/i/o/h XAIGER extensions 2019-04-17 10:55:23 -07:00
Eddie Hung fecafb2207 Forgot backslashes 2019-04-12 18:22:44 -07:00
Eddie Hung 9bfcd80063 Handle __dummy_o__ and __const[01]__ in read_aiger not abc 2019-04-12 18:21:16 -07:00
Eddie Hung c776db3320 Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-04-12 17:09:24 -07:00
Eddie Hung acf3f5694b Fix inout handling for -map option 2019-04-12 17:02:24 -07:00
Eddie Hung ada130b459 Also cope with duplicated CIs 2019-04-12 16:17:12 -07:00
Eddie Hung 1c6f0cffd9 Cope with an output having same name as an input (i.e. CO) 2019-04-12 12:27:07 -07:00
Eddie Hung 1a49cf29d8 parse_aiger() to rename all $lut cells after "clean" 2019-04-10 14:02:23 -07:00
Zachary Snow 5855024ccc support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
Eddie Hung 36efec01b8 Fix spacing 2019-04-08 16:37:22 -07:00
Eddie Hung bca3cf6843 Merge branch 'master' into xaig 2019-04-08 16:31:59 -07:00
Clifford Wolf dfb242c905 Add "read_ilang -lib" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-05 17:31:49 +02:00
Clifford Wolf 584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-29 16:32:44 +01:00
Clifford Wolf 7682629b79 Add "read -verific" and "read -noverific" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-27 14:03:35 +01:00
Clifford Wolf c863796e9f Fix "verific -extnets" for more complex situations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-26 14:17:46 +01:00
Clifford Wolf 638be461c3 Fix mem2reg handling of memories with upto data ports, fixes #888 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:21:17 +01:00
Clifford Wolf da42f10765 Improve "read_verilog -dump_vlog[12]" handling of upto ranges 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:20:16 +01:00
Clifford Wolf 9b0e7af6d7 Improve read_verilog debug output capabilities 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 20:52:29 +01:00
Eddie Hung 02e8dc7ad2 Merge https://github.com/YosysHQ/yosys into read_aiger 2019-03-19 08:52:31 -07:00
Eddie Hung 3e89cf68bd Add author name 2019-03-19 08:52:06 -07:00
Zachary Snow a5f4b83637 fix local name resolution in prefix constructs 2019-03-18 20:43:20 -04:00
Clifford Wolf 17caaa3fa8 Improve handling of "full_case" attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 17:51:21 +01:00
Clifford Wolf d25a0c8ade Improve handling of memories used in mem index expressions on LHS of an assignment 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:12:02 +01:00
Clifford Wolf a4ddc569b4 Remove outdated "blocking assignment to memory" warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:10:55 +01:00
Clifford Wolf ab5b50ae3c Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:09:47 +01:00
Clifford Wolf b02d9c2634 Fix handling of cases that look like sva labels, fixes #862 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-10 16:27:18 -07:00
Clifford Wolf cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels 
Add support for using SVA labels in yosys-smtbmc console output
 2019-03-09 11:14:57 -08:00