mirror of https://github.com/YosysHQ/yosys.git
remove leftovers from ast data structures
This commit is contained in:
parent
ed625a3102
commit
cd12f2ddcf
|
@ -51,7 +51,6 @@ namespace AST_INTERNAL {
|
|||
std::map<std::string, AstNode*> current_scope;
|
||||
const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
|
||||
RTLIL::SigSpec ignoreThisSignalsInInitial;
|
||||
std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
|
||||
AstNode *current_always, *current_top_block, *current_block, *current_block_child;
|
||||
AstModule *current_module;
|
||||
bool current_always_clocked;
|
||||
|
@ -943,8 +942,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
|
|||
log("--- END OF AST DUMP ---\n");
|
||||
}
|
||||
|
||||
wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>();
|
||||
|
||||
if (!defer)
|
||||
{
|
||||
bool blackbox_module = flag_lib;
|
||||
|
|
|
@ -327,7 +327,6 @@ namespace AST_INTERNAL
|
|||
extern std::map<std::string, AST::AstNode*> current_scope;
|
||||
extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
|
||||
extern RTLIL::SigSpec ignoreThisSignalsInInitial;
|
||||
extern std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
|
||||
extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;
|
||||
extern AST::AstModule *current_module;
|
||||
extern bool current_always_clocked;
|
||||
|
|
Loading…
Reference in New Issue