mirror of https://github.com/YosysHQ/yosys.git
Checking and fixing specify cells in genRTLIL
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -1521,9 +1521,23 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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for (auto &attr : attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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if (cell->type.in("$specify2", "$specify3")) {
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int src_width = GetSize(cell->getPort("\\SRC"));
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int dst_width = GetSize(cell->getPort("\\DST"));
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bool full = cell->getParam("\\FULL").as_bool();
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if (!full && src_width != dst_width)
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log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n");
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if (cell->type == "$specify3") {
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int dat_width = GetSize(cell->getPort("\\DAT"));
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if (dat_width != dst_width)
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log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n");
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}
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cell->setParam("\\SRC_WIDTH", Const(src_width));
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cell->setParam("\\DST_WIDTH", Const(dst_width));
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}
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}
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break;
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