mirror of https://github.com/YosysHQ/yosys.git
For hier_tree::Elaborate() also include SV root modules (bind)
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@ -46,8 +46,7 @@ USING_YOSYS_NAMESPACE
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#include "VeriModule.h"
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#include "VeriWrite.h"
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#include "VhdlUnits.h"
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#include "HierTreeNode.h"
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#include "Message.h"
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#include "VeriLibrary.h"
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#ifdef __clang__
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#pragma clang diagnostic pop
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@ -1775,25 +1774,29 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
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netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
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}
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else {
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const Map *tree_tops = hier_tree::CreateHierarchicalTreeAll(&veri_libs, &vhdl_libs, &verific_params);
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HierTreeNode *node = tree_tops ? static_cast<HierTreeNode*>(tree_tops->GetValue(top.c_str())) : NULL;
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if (node) {
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Map specific_tops(STRING_HASH);
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specific_tops.Insert(top.c_str(), node);
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Array veri_modules, vhdl_units;
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if (node->HasBindChild()) {
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MapIter mi;
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const char *key;
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FOREACH_MAP_ITEM(tree_tops, mi, &key, &node) {
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if (!node->IsPackage()) continue;
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specific_tops.Insert(key, node);
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}
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if (veri_lib) {
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VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
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if (veri_module) {
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veri_modules.InsertLast(veri_module);
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}
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netlists = hier_tree::GenerateNetlists(&specific_tops);
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// Also elaborate all root modules since they may contain bind statements
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MapIter mi;
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FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
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if (!veri_module->IsRootModule()) continue;
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veri_modules.InsertLast(veri_module);
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}
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}
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hier_tree::DeleteHierarchicalTree();
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veri_file::DeleteInstantiatedClassValues();
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if (vhdl_lib) {
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VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
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if (vhdl_unit)
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vhdl_units.InsertLast(vhdl_unit);
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}
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netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
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}
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Netlist *nl;
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@ -2300,12 +2303,22 @@ struct VerificPass : public Pass {
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for (; argidx < GetSize(args); argidx++)
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{
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const char *name = args[argidx].c_str();
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VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
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VeriModule *veri_module = veri_file::GetModule(name);
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if (veri_module) {
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log("Adding Verilog module '%s' to elaboration queue.\n", name);
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veri_modules.InsertLast(veri_module);
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continue;
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if (veri_lib) {
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VeriModule *veri_module = veri_lib->GetModule(name, 1);
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if (veri_module) {
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log("Adding Verilog module '%s' to elaboration queue.\n", name);
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veri_modules.InsertLast(veri_module);
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continue;
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}
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// Also elaborate all root modules since they may contain bind statements
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MapIter mi;
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FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
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if (!veri_module->IsRootModule()) continue;
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veri_modules.InsertLast(veri_module);
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}
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}
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VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
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