mirror of https://github.com/YosysHQ/yosys.git
Fix verific_parameters construction, use attribute to mark top netlists
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@ -775,9 +775,9 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
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merge_past_ffs_clock(it.second, it.first.first, it.first.second);
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}
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void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo, bool top)
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void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo)
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{
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std::string netlist_name = top ? nl->CellBaseName() : nl->Owner()->Name();
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std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name();
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std::string module_name = nl->IsOperator() ? "$verific$" + netlist_name : RTLIL::escape_id(netlist_name);
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netlist = nl;
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@ -1768,7 +1768,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
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if (veri_lib) veri_libs.InsertLast(veri_lib);
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Map verific_params(STRING_HASH);
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for (auto i : parameters)
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for (const auto &i : parameters)
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verific_params.Insert(i.first.c_str(), i.second.c_str());
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if (top.empty()) {
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@ -1800,8 +1800,10 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
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int i;
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FOREACH_ARRAY_ITEM(netlists, i, nl) {
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if (top.empty() || nl->CellBaseName() == top)
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nl_todo.insert(nl);
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if (top.empty() && nl->CellBaseName() != top)
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continue;
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nl->AddAtt(new Att(" \\top", NULL));
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nl_todo.insert(nl);
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}
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delete netlists;
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@ -1817,7 +1819,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
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Netlist *nl = *nl_todo.begin();
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if (nl_done.count(nl) == 0) {
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VerificImporter importer(false, false, false, false, false, false);
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importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == top);
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importer.import_netlist(design, nl, nl_todo);
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}
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nl_todo.erase(nl);
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nl_done.insert(nl);
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@ -2322,8 +2324,10 @@ struct VerificPass : public Pass {
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Netlist *nl;
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int i;
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FOREACH_ARRAY_ITEM(netlists, i, nl)
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FOREACH_ARRAY_ITEM(netlists, i, nl) {
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nl->AddAtt(new Att(" \\top", NULL));
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nl_todo.insert(nl);
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}
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delete netlists;
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}
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@ -93,7 +93,7 @@ struct VerificImporter
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void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol);
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void merge_past_ffs(pool<RTLIL::Cell*> &candidates);
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void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo, bool top=false);
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void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo);
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};
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void verific_import_sva_assert(VerificImporter *importer, Verific::Instance *inst);
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