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Merge pull request #1060 from antmicro/parsing_attr_on_port_conn 

Added support for parsing attributes on port connections.
This commit is contained in:
Clifford Wolf 2019-06-06 12:34:05 +02:00 committed by GitHub
parent 30cedaca10 03e0d3a17c
commit b894187cf6
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
14 changed files with 279 additions and 10 deletions
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24
frontends/verilog/verilog_parser.y
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@ -1532,27 +1532,31 @@ cell_port_list_rules:
cell_port | cell_port_list_rules ',' cell_port;
cell_port:
/* empty */ {
attr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
free_attr($1);
} |
expr {
attr expr {
AstNode *node = new AstNode(AST_ARGUMENT);
astbuf2->children.push_back(node);
node->children.push_back($1);
node->children.push_back($2);
free_attr($1);
} |
'.' TOK_ID '(' expr ')' {
attr '.' TOK_ID '(' expr ')' {
AstNode *node = new AstNode(AST_ARGUMENT);
node->str = *$2;
node->str = *$3;
astbuf2->children.push_back(node);
node->children.push_back($4);
delete $2;
node->children.push_back($5);
delete $3;
free_attr($1);
} |
'.' TOK_ID '(' ')' {
attr '.' TOK_ID '(' ')' {
AstNode *node = new AstNode(AST_ARGUMENT);
node->str = *$2;
node->str = *$3;
astbuf2->children.push_back(node);
delete $2;
delete $3;
free_attr($1);
};
always_stmt:

21
tests/simple/attrib01_module.v Normal file
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@ -0,0 +1,21 @@
module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (clk, rst, inp, out);
endmodule

25
tests/simple/attrib02_port_decl.v Normal file
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@ -0,0 +1,25 @@
module bar(clk, rst, inp, out);
(* this_is_clock = 1 *)
input wire clk;
(* this_is_reset = 1 *)
input wire rst;
input wire inp;
(* an_output_register = 1*)
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
(* this_is_the_master_clock *)
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (clk, rst, inp, out);
endmodule

28
tests/simple/attrib03_parameter.v Normal file
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@ -0,0 +1,28 @@
module bar(clk, rst, inp, out);
(* bus_width *)
parameter WIDTH = 2;
(* an_attribute_on_localparam = 55 *)
localparam INCREMENT = 5;
input wire clk;
input wire rst;
input wire [WIDTH-1:0] inp;
output reg [WIDTH-1:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= inp + INCREMENT;
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire [7:0] inp;
output wire [7:0] out;
bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
endmodule

32
tests/simple/attrib04_net_var.v Normal file
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@ -0,0 +1,32 @@
module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
(* this_is_a_prescaler *)
reg [7:0] counter;
(* temp_wire *)
wire out_val;
always @(posedge clk)
counter <= counter + 1;
assign out_val = inp ^ counter[4];
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= out_val;
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (clk, rst, inp, out);
endmodule

21
tests/simple/attrib05_port_conn.v.DISABLED Normal file
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@ -0,0 +1,21 @@
module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
endmodule

23
tests/simple/attrib06_operator_suffix.v Normal file
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@ -0,0 +1,23 @@
module bar(clk, rst, inp_a, inp_b, out);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output reg [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= inp_a + (* ripple_adder *) inp_b;
endmodule
module foo(clk, rst, inp_a, inp_b, out);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output wire [7:0] out;
bar bar_instance (clk, rst, inp_a, inp_b, out);
endmodule

21
tests/simple/attrib07_func_call.v.DISABLED Normal file
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@ -0,0 +1,21 @@
function [7:0] do_add;
input [7:0] inp_a;
input [7:0] inp_b;
do_add = inp_a + inp_b;
endfunction
module foo(clk, rst, inp_a, inp_b, out);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output wire [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= do_add (* combinational_adder *) (inp_a, inp_b);
endmodule

22
tests/simple/attrib08_mod_inst.v Normal file
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@ -0,0 +1,22 @@
module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
(* my_module_instance = 99 *)
bar bar_instance (clk, rst, inp, out);
endmodule

26
tests/simple/attrib09_case.v Normal file
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@ -0,0 +1,26 @@
module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire [1:0] inp;
output reg [1:0] out;
always @(inp)
(* full_case, parallel_case *)
case(inp)
2'd0: out <= 2'd3;
2'd1: out <= 2'd2;
2'd2: out <= 2'd1;
2'd3: out <= 2'd0;
endcase
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire [1:0] inp;
output wire [1:0] out;
bar bar_instance (clk, rst, inp, out);
endmodule

21
tests/various/attrib05_port_conn.v Normal file
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@ -0,0 +1,21 @@
module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
endmodule

2
tests/various/attrib05_port_conn.ys Normal file
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@ -0,0 +1,2 @@
# Read and parse Verilog file
read_verilog attrib05_port_conn.v

21
tests/various/attrib07_func_call.v Normal file
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@ -0,0 +1,21 @@
function [7:0] do_add;
input [7:0] inp_a;
input [7:0] inp_b;
do_add = inp_a + inp_b;
endfunction
module foo(clk, rst, inp_a, inp_b, out);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output wire [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= do_add (* combinational_adder *) (inp_a, inp_b);
endmodule

2
tests/various/attrib07_func_call.ys Normal file
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@ -0,0 +1,2 @@
# Read and parse Verilog file
read_verilog attrib07_func_call.v