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yosys
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191 Commits

Author SHA1 Message Date
Eddie Hung 2ef2aa997c read_aiger to not require clk_name for latches, plus debug 2019-06-15 09:07:53 -07:00
Eddie Hung 7876b5b8be Cover __APPLE__ too for little to big endian 2019-06-14 12:40:51 -07:00
Eddie Hung a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Eddie Hung 97d2656375 Resolve comments from @daveshah1 2019-06-14 12:00:02 -07:00
Eddie Hung a3be25ab0d Cleanup 2019-06-14 10:27:30 -07:00
Eddie Hung d005568f2e Add TODO to parse_xaiger 2019-06-14 10:11:13 -07:00
Eddie Hung bc22e2e3ee Optimise some more 2019-06-13 17:02:58 -07:00
Eddie Hung d09d4e0706 Move ConstEvalAig to aigerparse.cc 2019-06-13 16:28:11 -07:00
Eddie Hung d39a5a77a9 Add ConstEvalAig specialised for AIGs 2019-06-13 13:13:48 -07:00
Eddie Hung 342fc0a600 parse_xaiger to cope with inouts 2019-06-12 15:45:46 -07:00
Eddie Hung b21d29598a Consistency 2019-06-12 09:40:51 -07:00
Eddie Hung f7a9769c14 Merge remote-tracking branch 'origin/master' into xaig 2019-06-12 08:50:39 -07:00
Eddie Hung 2b350401c4 Fix spacing from spaces to tabs 2019-06-07 15:44:57 -07:00
Eddie Hung 6934f4bdd5 Fix spacing (entire file is wrong anyway, will fix later) 2019-06-07 11:30:36 -07:00
Eddie Hung d00ae1d6a8 Remove unnecessary std::getline() for ASCII 2019-06-07 11:28:25 -07:00
Eddie Hung a04521c6b7 Fix read_aiger -- create zero driver, fix init width, parse 'b' 2019-06-07 11:07:15 -07:00
Eddie Hung 7057753427 Rename label 2019-05-21 18:20:31 -07:00
Eddie Hung b5a29460b9 Try again 2019-05-21 17:20:19 -07:00
Eddie Hung 1bff09f2ff Fix warning 2019-05-21 16:26:20 -07:00
Eddie Hung d9c915042a Move clean from aigerparse to abc9 2019-04-23 13:42:35 -07:00
Eddie Hung 5f30a8795d Tidy up 2019-04-22 17:47:05 -07:00
Eddie Hung 8f30019b68 Revert "Temporarily remove 'r' extension" 
This reverts commit eaf3c24772.
 2019-04-22 17:41:21 -07:00
Eddie Hung eaf3c24772 Temporarily remove 'r' extension 2019-04-22 11:54:19 -07:00
Eddie Hung 4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Clifford Wolf e158ea2097 Add log_debug() framework 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 17:25:52 +02:00
Eddie Hung 21701cc1df read_aiger to parse 'r' extension 2019-04-18 17:39:36 -07:00
Eddie Hung e1b550d203 Ignore a/i/o/h XAIGER extensions 2019-04-17 10:55:23 -07:00
Eddie Hung fecafb2207 Forgot backslashes 2019-04-12 18:22:44 -07:00
Eddie Hung 9bfcd80063 Handle __dummy_o__ and __const[01]__ in read_aiger not abc 2019-04-12 18:21:16 -07:00
Eddie Hung c776db3320 Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-04-12 17:09:24 -07:00
Eddie Hung acf3f5694b Fix inout handling for -map option 2019-04-12 17:02:24 -07:00
Eddie Hung ada130b459 Also cope with duplicated CIs 2019-04-12 16:17:12 -07:00
Eddie Hung 1c6f0cffd9 Cope with an output having same name as an input (i.e. CO) 2019-04-12 12:27:07 -07:00
Eddie Hung 1a49cf29d8 parse_aiger() to rename all $lut cells after "clean" 2019-04-10 14:02:23 -07:00
Eddie Hung 36efec01b8 Fix spacing 2019-04-08 16:37:22 -07:00
Eddie Hung da076344cc parse_xaiger() to really pass single and multi-bit inout tests 2019-02-26 12:04:45 -08:00
Eddie Hung 8f02c846f6 parse_xaiger() to cope with multi bit inouts 2019-02-26 11:37:34 -08:00
Eddie Hung 316232a7dd parse_xaiger() to untransform $inout.out output ports 2019-02-25 18:40:23 -08:00
Eddie Hung 721f6a14fb read_aiger to accept empty string for clk_name, passable only if no latches 2019-02-25 15:34:02 -08:00
Eddie Hung 07036b8bf7 read_aiger to work with symbol table 2019-02-21 17:01:07 -08:00
Eddie Hung 085ed9f487 Add attribution 2019-02-21 14:40:13 -08:00
Eddie Hung 3307295488 Merge branch 'read_aiger' into xaig 2019-02-21 14:27:32 -08:00
Eddie Hung 9e299a0908 read_aiger to not do -purge for clean 2019-02-20 17:33:04 -08:00
Eddie Hung 32853b1f8d lut/not/and suffix to be ${lut,not,and} 2019-02-20 16:30:30 -08:00
Eddie Hung abc1c2672e read_aiger to also rename 0 index lut when wideports 2019-02-20 16:17:22 -08:00
Eddie Hung f9702a8abe read_aiger: new naming fixes 2019-02-20 12:39:51 -08:00
Eddie Hung 83b66861e9 read_aiger to name wires with internal name, less likely to clash 2019-02-20 11:22:56 -08:00
Eddie Hung 7b026c4bc3 Same for ascii AIGERs too 2019-02-19 15:15:50 -08:00
Eddie Hung d304882cba read_aiger to cope with non-unique POs 2019-02-19 15:14:08 -08:00
Eddie Hung e79df5e70e read_aiger to create sane $lut names, and rename when renaming driving wire 2019-02-19 12:27:50 -08:00
Eddie Hung 0b1fc46ae3 Add comment 2019-02-19 10:24:55 -08:00
Eddie Hung 54f719f446 Get rid of boost dep, fix the FIXMEs for Win32? 2019-02-19 10:19:53 -08:00
Eddie Hung 843e7fc8a7 Fix for using POSIX basename 2019-02-19 09:02:37 -08:00
Eddie Hung 8e1dbfac3a Missing OSX headers? 2019-02-17 20:59:53 -08:00
Eddie Hung 9268a271fb read_aiger to ignore line after ands for ascii, not binary 2019-02-17 12:07:14 -08:00
Eddie Hung 82459c16c4 In read_xaiger, do not construct ConstEval for every LUT 2019-02-16 22:22:29 -08:00
Eddie Hung f60cd4ff9b read_aiger to ignore output = input of same wire; also create new output for different wire 2019-02-16 21:53:03 -08:00
Eddie Hung 1a25ec4baa read_aiger to disable log_debug 2019-02-16 13:45:51 -08:00
Eddie Hung 8f36013fac read_xaiger() to use f.read() not readsome() 2019-02-16 08:58:25 -08:00
Eddie Hung 7523c87780 read_aiger() to cope with constant outputs, mixed wideports, do cleaning 2019-02-16 08:44:11 -08:00
Eddie Hung 8d757224ee read_aiger with more asserts, and call clean 2019-02-15 11:52:05 -08:00
Eddie Hung c7ef3863f3 Leave FIXME for clean 2019-02-13 17:19:30 -08:00
Eddie Hung 396da54b52 Use module->addLut() 2019-02-13 17:08:32 -08:00
Eddie Hung 13bf036bd6 Use ConstEval to compute LUT masks 2019-02-13 17:00:00 -08:00
Eddie Hung f0f5d8a5cc Merge remote-tracking branch 'origin/read_aiger' into xaig 2019-02-13 14:09:36 -08:00
Eddie Hung e9df9a466a Add support for read_aiger -wideports 2019-02-12 12:58:10 -08:00
Eddie Hung 06ba81d41f Add support for read_aiger -map 2019-02-12 12:16:37 -08:00
Eddie Hung 77d3627753 Parse 'm' in xaiger 2019-02-12 09:36:22 -08:00
Eddie Hung 6faad18874 Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger 2019-02-12 09:21:46 -08:00
Eddie Hung a2ae393811 Use module->add{Not,And}Gate() functions 2019-02-12 09:21:15 -08:00
Eddie Hung 0124512f28 Add read_xaiger 2019-02-11 15:19:17 -08:00
Eddie Hung 04c580fde7 Do not break for constraints 2019-02-11 13:28:00 -08:00
Eddie Hung 727ba52504 No increment line_count for binary ANDs 2019-02-11 13:24:21 -08:00
Eddie Hung bb4164481d Do not ignore newline after AND in binary AIG 2019-02-11 11:51:44 -08:00
Eddie Hung 8886fa5506 addDff -> addDffGate as per @daveshah1 2019-02-08 13:17:53 -08:00
Eddie Hung afc3c4b613 Fix tabulation 2019-02-08 13:17:02 -08:00
Eddie Hung aa66d8f12f -module_name arg to go before -clk_name 2019-02-08 12:49:55 -08:00
Eddie Hung fb8ad440a3 Allow module name to be determined by argument too 2019-02-08 12:40:43 -08:00
Eddie Hung f1befe1b44 Refactor into AigerReader class 2019-02-08 12:04:26 -08:00
Eddie Hung 2a8cc36578 Parse binary AIG files 2019-02-08 11:45:16 -08:00
Eddie Hung 09d758f0a3 Refactor to parse_aiger_header() 2019-02-08 10:54:31 -08:00
Eddie Hung 36c56bf412 Add comment 2019-02-08 08:37:44 -08:00
Eddie Hung 5e24251a61 Handle reset logic in latches 2019-02-08 08:37:18 -08:00
Eddie Hung 652e414392 Change literal vars from int to unsigned 2019-02-08 08:09:30 -08:00
Eddie Hung fafa972238 Create clk outside of latch loop 2019-02-08 08:08:49 -08:00
Eddie Hung 02f603ac1a Handle latch symbols too 2019-02-08 08:05:27 -08:00
Eddie Hung 5a593ff41c Remove return after log_error 2019-02-08 08:04:48 -08:00
Eddie Hung 6dbeda1807 Add support for symbol tables 2019-02-08 08:03:40 -08:00
Eddie Hung 791f93181d Stub for binary AIGER 2019-02-08 07:31:04 -08:00
Eddie Hung 40db2f2eb6 Refactor 2019-02-06 14:58:47 -08:00
Eddie Hung cc0b723484 WIP 2019-02-06 12:19:48 -08:00