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Change literal vars from int to unsigned
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@ -100,7 +100,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
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return wire;
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};
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int l1, l2, l3;
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unsigned l1, l2, l3;
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// Parse inputs
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std::vector<RTLIL::Wire*> inputs;
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