a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-06 07:22:17 +00:00
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
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frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
e936ac61ea
ast: swap range regardless of range_left >= 0
2020-05-04 12:18:20 -07:00
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
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frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
a0afa1787e
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
88185f8959
Fix handling of signed indices in bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbde241942
Merge pull request #2001 from whitequark/wasi
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Add WASI platform support
2020-05-01 21:28:20 +00:00
d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837
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Clear current_scope when done with RTLIL generation
2020-05-01 14:58:41 +02:00
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
5017ff4a97
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
97bfe65d3a
verific: support VHDL enums too
2020-04-27 15:17:13 -07:00
adb483ddfd
frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire
2020-04-27 10:36:18 -07:00
5f9cd2e2f6
Preserve 'signed'-ness of a verilog wire through RTLIL
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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987 , now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
dd5f206d9e
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-27 08:43:54 -07:00
b52eccef3a
Revert "verific: import enum attributes from verific"
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This reverts commit 5028e17f7d
2020-04-24 11:57:55 -07:00
d3555c667c
verific: do not assert if wire not found; warn instead
2020-04-23 16:28:11 -07:00
5028e17f7d
verific: import enum attributes from verific
2020-04-22 17:26:56 -07:00
9f1fb11b1d
Clear current_scope when done with RTLIL generation, fixes #1837
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-22 14:51:20 +02:00
06a344efcb
ilang, ast: Store parameter order and default value information.
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Fixes #1819 , #1820 .
2020-04-21 19:09:00 +02:00
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
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Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name
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ast, rpc: record original name of $paramod\* as \hdlname attribute
2020-04-21 01:43:20 +00:00
35990b95ec
Extend support for format strings in Verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-18 14:08:51 +02:00
41421f5dca
ast, rpc: record original name of $paramod\* as \hdlname attribute.
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The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.
This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
00d74f0b9c
Set Verilog source location for explicit blocks (`begin` ... `end`).
2020-04-17 06:23:03 +00:00
10a814f978
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
2020-04-17 06:16:59 +00:00
9253497358
Add location information to `AST_CONSTANT` nodes.
2020-04-16 19:11:47 +00:00
e86ba3b94d
Make mask-and-shift the default for bitselwrite
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:52 +02:00
e1fb12a4b9
Add LookaheadRewriter for proper bitselwrite support
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
4711fea6c0
Improved rewrite code for writing to bit slice (disabled for now)
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This adds the new rewrite rule. But it's still missing a check that makes
sure the new rewrite rule is actually a valid substitute in the always
block being processed. Therefore the new rewrite rule is just disabled
for now.
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-15 17:44:37 +02:00
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
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ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
2106f78bb1
ast/simplify: improve enum handling.
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Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
9b4dab397e
Fix 5bba9c3, closes #1876
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-14 21:05:07 +02:00
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
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support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
0e1beb6f30
Merge pull request #1880 from jjj11x/duplicate_enum
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duplicated enum item names should result in an error
2020-04-14 12:39:28 +00:00
5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser
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Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 08:40:45 +00:00
8a84674a42
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 04:22:00 +00:00
0a178de1b3
verilog: Fix write to deleted object
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-12 18:49:09 +01:00
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow
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Improve handling of integer literals in RTLIL frontend
2020-04-09 04:02:57 +00:00
c15040c218
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
b494d4c656
read_ilang: improve style. NFC.
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Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-06 18:31:15 +00:00
d22888ce74
read_ilang: improve error message for overly long wires.
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Fixes #1838 .
2020-04-06 10:33:02 +00:00
ca70a1049f
read_ilang: detect overflow of integer literals.
2020-04-06 10:32:02 +00:00
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
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ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-02 12:27:10 -07:00
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
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IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
c69f4b246a
Merge pull request #1846 from dh73/ast_fe
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Adding error message for when size (width) of number literal is zero
2020-04-02 18:15:15 +02:00
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc
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verilog: Add location info for generate constructs
2020-04-01 20:55:24 +01:00
c3997c77a5
verilog: Add location info for generate constructs
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-01 18:47:20 +01:00
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
c859bcf71b
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
92809bb1d3
Adding error message for when size (width) of number literal is zero
2020-03-30 17:18:13 -06:00
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
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Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines
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Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
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ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
f8c065ed1c
Inline productions to follow house style.
2020-03-27 16:21:45 +00:00
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
6040593994
Revert over-aggressive change to a more modest cleanup.
2020-03-27 09:46:40 +00:00
9a8a644ad1
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
6cad865d12
Simplify was not being called for packages. Broke typedef enums.
2020-03-22 18:20:46 -07:00
c06eda2504
Build pkg_user_types before parsing in case of changes in the design.
2020-03-22 18:20:46 -07:00
0aaa36ca6d
Clear pkg_user_types if no packages following a 'design -reset-vlog'.
2020-03-22 18:20:46 -07:00
14f32028ec
Parser changes to support typedef.
2020-03-22 18:20:46 -07:00
f828cb5132
Merge pull request #1788 from YosysHQ/eddie/fix_ndebug
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Fix NDEBUG warnings
2020-03-19 14:58:06 -07:00
d46259becd
Merge pull request #1787 from YosysHQ/mmicko/lexer_deps
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Add dependency to verilog_lexer.cc
2020-03-19 18:24:40 +01:00
dc75ed7dac
Add one mode dependency
2020-03-19 16:53:40 +01:00
43092f063f
Fix NDEBUG warnings
2020-03-19 08:48:39 -07:00
b473264a06
Merge pull request #1775 from huaixv/asserts_locations
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Add precise locations for asserts
2020-03-19 13:12:18 +01:00
eb30d66d01
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-19 07:29:00 +00:00
cd82ccd258
Add precise locations for asserts
2020-03-19 10:22:07 +08:00
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
6dd2024965
Add AST node source location information in a couple more parser rules.
2020-03-17 06:22:12 +00:00
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
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refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations
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Set AST node source location in more parser rules.
2020-03-14 11:18:39 +02:00
5e94bf0291
refixed parsing of constant with comment between size and value
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The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
2020-03-11 18:21:44 +01:00
7b679eecb3
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
2d63bf5877
verilog: also set location for simple_behavioral_stmt
2020-03-10 10:29:24 -07:00
da8270aa01
Set AST source locations in more parser rules.
2020-03-10 01:50:39 +00:00
a7cc4673c3
Fix partsel expr bit width handling and add test case
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
d59da5a4e4
Fix bison warning for "pure-parser" option
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-03 08:41:55 -08:00
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
91892465e1
Merge pull request #1681 from YosysHQ/eddie/fix1663
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verilog: instead of modifying localparam size, extend init constant expr
2020-03-03 08:34:31 -08:00
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
825b96fdcf
Comment out log()
2020-02-27 16:53:49 -08:00
e79376d6cb
ast: quiet down when deriving blackbox modules
2020-02-27 10:17:29 -08:00
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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Enum support
2020-02-20 18:17:25 +01:00
ea4bd161b6
verilog: add support for more delays than just rise/fall
2020-02-19 11:09:37 -08:00
a31ba8e5d5
remove unnecessary blank line
2020-02-17 04:42:49 -05:00
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
6320f2692b
separate out enum_item/param implementation when they should be different
2020-02-17 04:42:30 -05:00
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
6b58c1820c
verilog: improve specify support when not in -specify mode
2020-02-13 13:27:15 -08:00
2e51dc1856
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
7cfdf4ffa7
verilog: fix $specify3 check
2020-02-13 12:42:04 -08:00
e069259a53
Merge pull request #1679 from thasti/delay-parsing
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Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
c34d7b13f4
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
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Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-02-07 00:41:54 +00:00
da485dc007
Modified $readmem[hb] to use '\' or '/' according the OS
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Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:10:29 -03:00
fc33287bc1
verilog: instead of modifying localparam size, extend init constant expr
2020-02-05 17:19:42 -08:00
b844b078db
correct wire declaration grammar for #1614
2020-02-03 21:29:40 +01:00
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
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Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
71f3afb9a2
Replaced strlen by GetSize into simplify.cc
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As recommended in CodingReadme.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:44:09 -03:00
4bfd2ef4f3
sv: Improve handling of wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
5df591c023
hierarchy: Resolve SV wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
50f86c11b2
sv: Add lexing and parsing of .* (wildcard port conns)
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf
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ast: Add support for $sformatf system function
2020-02-02 14:53:46 +00:00
b4c30cfc8d
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:03:56 -03:00
d74b9604e3
Modified the new search for files of $readmem[hb] to be backward compatible
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 22:10:51 -03:00
7b3fe404ab
$readmem[hb] file inclusion is now relative to the Verilog file
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 18:20:22 -03:00
2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand
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Add Verific support for OPER_REDUCE_NAND
2020-01-30 19:55:53 +01:00
60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help
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`verific` pass to print help message when command syntax error
2020-01-30 18:05:16 +01:00
ffadaddab5
Merge pull request #1654 from YosysHQ/eddie/sby_fix69
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verific: unflatten struct ports
2020-01-30 18:03:35 +01:00
23c44afaed
Add Verific support for OPER_REDUCE_NAND
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-30 18:01:13 +01:00
6d27d43727
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
ce6a690d27
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
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Now done in read_aiger
2020-01-27 13:30:27 -08:00
f443695a38
Merge remote-tracking branch 'origin/master' into eddie/verific_help
2020-01-27 10:34:10 -08:00
d730bba6d2
verific: no help() when no YOSYS_ENABLE_VERIFIC
2020-01-27 10:32:18 -08:00
7b445121cc
verific: also unflatten for 'hierarchy' flow as per @cliffordwolf
2020-01-27 10:15:22 -08:00
c7fbe13db5
read_aiger: set abc9_box_seq attr
2020-01-24 13:11:43 -08:00
cccc0ae112
verific: unflatten struct ports
2020-01-24 10:12:52 -08:00
73526a6f10
read_aiger: also parse abc9_mergeability
2020-01-22 14:21:25 -08:00
cd093c00f8
read_aiger: discard LUT inputs with nodeID == 0; not < 2
2020-01-21 11:56:30 -08:00
7f728bc116
read_aiger: ignore constant inputs on LUTs
2020-01-21 11:16:50 -08:00
22c967e35e
ast: Add support for $sformatf system function
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Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
98c6bd7630
fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6
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The if(str == node->str) is in fact necessary (otherwise causes generate
for in Multiplier_2D in tests/simple/multiplier.v to fail with error
message "Right hand side of 3rd expression of generate for-loop is not
constant!"). Note: in PeterCrozier's implementation, the break only
breaks out of the switch-case, not the outer for loop.
2020-01-17 02:07:42 -05:00
549deb6373
fix enum in generate blocks
2020-01-16 18:13:30 -05:00
41a0a93dcc
allow enums to be declared at toplevel scope
2020-01-16 18:13:14 -05:00
cc2236d0c0
lexer doesn't seem to return TOK_REG for logic anymore
2020-01-16 18:08:58 -05:00
Eddie Hung
Zachary Snow
Alberto Gonzalez
whitequark
Claire Wolf
Claire Wolf
Vamsi K Vytla
Marcelina Kościelnicka
David Shah
Henner Zeller
Jeff Wang
Diego H
N. Engelhardt
Peter Crozier
Rupert Swarbrick
Miodrag Milanović
huaixv
Marcus Comstedt
jiegec
Rodrigo Alejandro Melo
Stefan Biereigel
Rodrigo Alejandro Melo