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10162 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 082cbcb4c7 synth_intel: Remove incomplete Arria 10 GX support. 
The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
 2020-08-21 01:46:06 +02:00
Dan Ravensloft 034b9ec716 intel: move Cyclone V support to intel_alm 2020-08-20 18:25:05 +02:00
clairexen d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes 
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
 2020-08-20 16:25:56 +02:00
clairexen a96df40814
Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes 
opt_share: Refactor, fix some bugs.
 2020-08-20 16:24:53 +02:00
clairexen 1d0d9d5c86
Merge pull request #2337 from YosysHQ/mwk/clean-keep-wire 
opt_clean: Fix module keep rules.
 2020-08-20 16:23:55 +02:00
clairexen 799076af24
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed 
peeopt.shiftmul: Add a signedness check.
 2020-08-20 16:23:07 +02:00
clairexen 6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup 
Remove passes redundant with opt_dff
 2020-08-20 16:21:58 +02:00
clairexen faf8e19511
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix 
techmap.CONSTMAP: Handle outputs before inputs.
 2020-08-20 16:21:09 +02:00
clairexen 16bb3fc8bb
Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign 
peepopt.muldiv: Add a signedness check.
 2020-08-20 16:19:37 +02:00
clairexen 1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern 
techmap: Add support for [] wildcards in techmap_celltype.
 2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka 50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path. 
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
 2020-08-20 12:44:09 +02:00
Yosys Bot 23719ad46d Bump version 2020-08-20 00:10:07 +00:00
clairexen 87b9ee330d
Merge pull request #2122 from PeterCrozier/struct_array2 
Support 2D bit arrays in structures. Optimise array indexing.
 2020-08-19 17:58:37 +02:00
Yosys Bot 93d663be62 Bump version 2020-08-19 00:10:09 +00:00
Xiretza 916028906a Ensure \A_SIGNED is never used with $shiftx 
It has no effect on the output ($shiftx doesn't perform any sign
extension whatsoever), so an attempt to use it should be caught early.
 2020-08-18 19:36:24 +02:00
Xiretza 928fd40c2e Respect \A_SIGNED for $shift 
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
 2020-08-18 19:36:24 +02:00
N. Engelhardt 850f66cfdd include both power-of-two and non-power-of-two testcases 2020-08-18 18:54:22 +02:00
clairexen 22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s 
Allow %0s $display format specifier
 2020-08-18 17:39:01 +02:00
clairexen 4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish 
Propagate const_fold through generate blocks and branches
 2020-08-18 17:38:07 +02:00
clairexen a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock 
Fix generate scoping issues
 2020-08-18 17:37:11 +02:00
Claire Wolf fce5f02a9d Merge branch 'zachjs-const-func-block-var' 2020-08-18 17:32:00 +02:00
Claire Wolf 7f767bf2b7 Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-08-18 17:29:49 +02:00
clairexen 5ee9349647
Merge pull request #2281 from zachjs/const-real 
Allow reals as constant function parameters
 2020-08-18 17:22:20 +02:00
Marcelina Kościelnicka 2b777bbda8 opt_share: Refactor, fix some bugs. 
Fixes #2334.
Fixes #2335.
Fixes #2336.
 2020-08-17 17:26:36 +02:00
Yosys Bot 3cb3978ff4 Bump version 2020-08-14 00:10:13 +00:00
Dan Ravensloft 3b534a203a intel_alm: fix typo in MISTRAL_MUL27X27 cell name 2020-08-13 17:08:50 +02:00
Yosys Bot f61d62a7bc Bump version 2020-08-13 00:10:08 +00:00
whitequark a74a43d85d
Merge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout 
cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False
 2020-08-12 20:02:18 +00:00
Andy Knowles 5829d16fcd
cxxrtl.h: Fix incorrect CarryOut in alu() 2020-08-12 21:04:34 +02:00
Dan Ravensloft 97daf612cb intel_alm: add more megafunctions. NFC. 2020-08-12 18:39:22 +02:00
Andy Knowles 1227c3681b cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False 2020-08-12 11:32:57 +02:00
Yosys Bot 04f6158bf2 Bump version 2020-08-10 09:30:51 +00:00
Zachary Snow 2ee0b8ebea Propagate const_fold through generate blocks and branches 2020-08-09 17:21:08 -04:00
Zachary Snow 96ec9acf84 Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
Marcelina Kościelnicka 2ab350a7b0 opt_clean: Fix module keep rules. 
- wires with keep attribute now force a module to be kept
- presence of $memwr and $meminit cells no longer forces a module to be
  kept
 2020-08-09 13:57:00 +02:00
Marcelina Kościelnicka 54a0c083a1 Remove now-redundant dff2dffe pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 5693386a4e Remove now-redundant dff2dffs pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka a0e99a9f3f peepopt: Remove now-redundant dffmux pattern. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka acd8c5c205 Remove now-redundant opt_rmdff pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka c1ed1c28be peeopt.shiftmul: Add a signedness check. 
Fixes #2332.
 2020-08-05 21:01:20 +02:00
Marcelina Kościelnicka b4a4cb081d techmap.CONSTMAP: Handle outputs before inputs. 
Fixes #2321.
 2020-08-05 12:28:18 +02:00
Marcelina Kościelnicka e89cc9c02f peepopt.muldiv: Add a signedness check. 
Fixes #2318.
 2020-08-04 16:30:24 +02:00
Marcelina Kościelnicka 522788f016 techmap: Add support for [] wildcards in techmap_celltype. 
Fixes #1826.
 2020-08-02 22:46:48 +02:00
Zachary Snow c3e95eb1ab Fix generate scoping issues 
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456
 2020-07-31 20:32:47 -06:00
Claire Wolf c39ebe6ae0 Bump YOSYS_VER 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-31 20:57:41 +02:00
Marcelina Kościelnicka 18ad56ef41 Add dffunmap pass. 
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
 2020-07-31 00:59:51 +02:00
Marcelina Kościelnicka 6cd135a5eb opt_expr: Remove -clkinv option, make it the default. 
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
 2020-07-31 00:08:15 +02:00
Marcelina Kościelnicka cf60699884 synth_ice40: Use opt_dff. 
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka 8501342fc5 synth_xilinx: Use opt_dff. 
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
 2020-07-30 22:26:09 +02:00