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Merge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout 

cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False
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whitequark 2020-08-12 20:02:18 +00:00 committed by GitHub
parent 97daf612cb 5829d16fcd
commit a74a43d85d
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1 changed files with 2 additions and 1 deletions
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backends/cxxrtl/cxxrtl.h
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@ -452,10 +452,11 @@ struct value : public expr_base<value<Bits>> {
bool carry = CarryIn;
for (size_t n = 0; n < result.chunks; n++) {
result.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;
if (result.chunks - 1 == n)
result.data[result.chunks - 1] &= result.msb_mask;
carry = (result.data[n] < data[n]) ||
(result.data[n] == data[n] && carry);
}
result.data[result.chunks - 1] &= result.msb_mask;
return {result, carry};
}