Martin Povišer
34572708d5
Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode
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internal_stats: astnode (sizeof)
2024-09-11 12:21:29 +02:00
Emil J. Tywoniak
1372c47036
internal_stats: astnode (sizeof)
2024-09-11 11:34:20 +02:00
Emil J. Tywoniak
8b464341c2
clockgate: no initvals
2024-09-11 10:24:48 +02:00
Roland Coeurjoly
bdc43c6592
Add left and right bound properties to wire. Add test. Fix printing
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for signed attributes
Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-09-10 12:52:42 +02:00
Emil J. Tywoniak
7e473299bd
clockgate: bail on constant signals
2024-09-09 21:20:19 +02:00
Emil J. Tywoniak
e64fceef70
clockgate: prototype clock gating
2024-09-09 15:00:54 +02:00
Hoa Nguyen
c1205ebc42
Initialize area stats in stat pass
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Currently, the area variables in the stat struct are not initialized.
This caused the area stats occasionally being an erroneous value.
Signed-off-by: Hoa Nguyen <hnpl@google.com>
2024-09-07 21:30:58 -07:00
Miodrag Milanović
b20df72e1e
Merge pull request #4536 from YosysHQ/functional
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Functional Backend
2024-09-06 10:05:04 +02:00
Emil J. Tywoniak
14b9155492
internal_stats: fix doc build by adding a help string
2024-09-05 11:22:21 +02:00
Martin Povišer
68fbca8769
Merge pull request #4554 from YosysHQ/emil/devstat
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internal_stats: init, report current memory consumption on linux and mac
2024-09-03 21:06:46 +02:00
Emil J. Tywoniak
0ce7631956
internal_stats: init, report current memory consumption on linux and mac
2024-09-03 19:28:24 +02:00
George Rennie
bdb5d45591
proc_dff: respect sync rule priorities when generating complex dffsrs
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* This fixes #4560 , where previously the order that sync rules were
processed in depended on the order they were pulled out of a std::map.
This PR changes this to process them in the order they are found in,
respecting the priorities among the async signals
2024-08-28 15:48:07 +01:00
N. Engelhardt
0fc5812dcd
Merge pull request #4541 from YosysHQ/krys/compiler-warnings
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Resolve (some) compiler warnings
2024-08-26 15:04:16 +02:00
Emily Schmidt
850b3a6c29
convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h
2024-08-21 11:04:08 +01:00
Emily Schmidt
8c0f625c3a
functional backend: topological sort starts with the output and next states nodes, other nodes get deleted
2024-08-21 11:03:29 +01:00
Emily Schmidt
bdb59ffc8e
add -fst-noinit flag to sim for not initializing the state from the fst file
2024-08-21 11:03:29 +01:00
Emily Schmidt
dd5ec84a26
fix bugs in drivertools
2024-08-21 11:01:09 +01:00
Jannis Harder
d4e3daa9d0
ComputeGraph datatype for the upcoming functional backend
2024-08-21 11:01:09 +01:00
Jannis Harder
68c3a47945
WIP temporary drivertools example
2024-08-21 11:01:08 +01:00
Emil J
e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix
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peepopt: avoid shift-amount underflow
2024-08-19 15:45:46 +02:00
Krystine Sherwin
7b47f645d7
Address warnings
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- Setting default values
- Fixing mismatched types
- Guarding unused var
2024-08-16 04:30:31 +12:00
Martin Povišer
3057c13a66
Improve libparse encapsulation
2024-08-13 18:47:36 +02:00
Martin Povišer
78382eaa6f
libparse: Adjust whitespace
2024-08-13 18:47:36 +02:00
Martin Povišer
4c3203866f
exec: Add missing newline
2024-08-07 13:02:00 +02:00
George Rennie
236c69bed4
clk2fflogic: run peepopt -formalclk before processing design
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* this attempts to rewrite clock gating patterns into a form that is
less likely to introduce combinational loops with clk2fflogic
* can be disabled with -nopeepopt which is useful for testing
clk2fflogic
2024-08-07 10:14:04 +01:00
George Rennie
2cb3b6e9b8
peepopt: add formal only peepopt to rewrite latches to ffs in clock gates
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* this is gated behind the -formalclk flag, which also disables the other
synthesis focused optimizations
2024-08-07 10:01:45 +01:00
Miodrag Milanovic
6d98418f3d
Set ranges on exported wires in VCD and FST
2024-08-02 15:23:00 +02:00
Emil J
92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy
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cost: add keep_hierarchy pass with min_cost argument
2024-07-29 16:33:08 +02:00
N. Engelhardt
9f869b265c
Merge pull request #4474 from tony-min-1/mchp
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Add PolarFire FPGA support
2024-07-29 15:28:44 +02:00
Emil J. Tywoniak
4b29f64142
cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
2024-07-29 10:26:02 +02:00
N. Engelhardt
dd3637f9f0
Merge pull request #4506 from povik/synthprop-formatting
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synthprop: Reformat the help
2024-07-26 12:28:09 +02:00
Martin Povišer
7ee685a0b0
proc_rom: Set `src` on the emitted memory
2024-07-25 23:14:27 +01:00
Martin Povišer
e063b96104
synthprop: Reformat the help
2024-07-25 11:43:58 +02:00
Martin Povišer
0cefe8a1e8
check: Skip detailed edge modeling if costly
2024-07-18 13:08:19 +02:00
Martin Povišer
e70b1251ad
check: Adjust prints
2024-07-18 13:08:19 +02:00
Martin Povišer
3f71bc469d
check: Rephrase comment
2024-07-18 13:08:19 +02:00
Emil J
1166238c0f
Merge pull request #4176 from povik/opt_expr-performance
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Improve `opt_expr` performance
2024-07-15 16:10:25 +02:00
Emil J. Tywoniak
532188f239
opt_expr: change info message
2024-07-15 11:14:47 +02:00
Tony Min
d41688f7d7
Revisions ( #4 )
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* area should be 1 for all LUTs
* clean up macros
* add log_assert to fail noisily when encountering oddly configured DFF
* clean help msg
* flatten set to true by default
* update
* merge mult tests
* remove redundant test
* move all dsp tests to single file and remove redundant tests
* update ram tests
* add more dff tests
* fix c++20 compile errors
* add option to dump verilog
* default to use abc9
* remove -abc9 option since its the default now
---------
Co-authored-by: tony <minchunlin@gmail.com>
2024-07-08 10:57:16 -04:00
N. Engelhardt
dac5bd1983
Merge pull request #4455 from phsauter/shiftadd-limit-padding
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peepopt: limit padding from shiftadd
2024-07-06 08:10:25 +02:00
C77874
d0cd01adfe
fixed typos, build with makefile succeeds
2024-07-04 09:33:58 -07:00
C77874
0bb7d1373f
changes made to filenames + references
2024-07-04 08:53:41 -07:00
Chun Lin Min
e5bdc9b5c9
remove DSP48 references
2024-07-03 07:20:29 -07:00
Chun Lin Min
2ced2752e9
replace space indent with tab indent
2024-07-02 13:47:18 -07:00
Chun Lin Min
acddc36389
add PolarFire FPGA support
2024-07-02 12:44:30 -07:00
Catherine
580aaa362d
opt_lut_ins: fix name of global object. NFCI
2024-06-28 15:12:36 +00:00
Emil J. Tywoniak
01f332e750
opt_expr: reduce mostly harmless warning to log
2024-06-25 20:18:49 +02:00
Martin Povišer
fa4a2b6b0d
opt_expr: In clkinv loop ignore irrelevant cells early
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Each call to `handle_clkpol_celltype_swap` has a conversion of the
cell's type ID to an allocated string. This can sum up to a
non-negligible time being spent in the clkpol code even for a design
which doesn't have any flip-flop gates.
2024-06-24 18:32:33 +02:00
Martin Povišer
7a8a69b65c
opt_expr: Revisit sorting in `replace_const_cells`
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Avoid building a cell-to-inbit map when sorting the cells, add a warning
if we are unable to sort, and move the code treating non-combinational
cells ahead of the rest (this means we don't need to pass
non-combinational cells to the TopoSort object at all).
2024-06-24 18:32:33 +02:00
Philippe Sauter
2f0f10cb87
peepopt: limit padding from shiftadd
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The input to a shift operation is padded.
This reduced the final number of MUX cells
but during techmap it can create huge
temporary multiplexers in the log shifter.
This significantly increases runtime and resources.
A limit is added with a warning when it is used.
2024-06-14 15:33:03 +02:00
Philippe Sauter
74e504330a
peepopt: fix sign check in shiftadd
2024-06-14 13:01:18 +02:00
phsauter
34b5c6d062
peepopt: avoid shift-amount underflow
2024-06-13 23:30:07 +02:00
George Rennie
41aaaa153e
peepopt shiftadd: Only match for sufficiently small constant widths
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This addresses issue #4445
2024-06-12 14:38:12 +01:00
Miodrag Milanovic
9b82a44d25
Fix help message typo
2024-06-07 08:26:59 +02:00
Martin Povišer
4b67f3757f
Merge pull request #4404 from YosysHQ/povik/bbox_derive
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box_derive: New command to derive modules for boxes
2024-05-31 19:09:18 +02:00
Martin Povišer
b230c95cc4
select: Adjust help
2024-05-29 20:41:56 +02:00
Martin Povišer
49906be776
select: Introduce `-assert-mod-count`
2024-05-21 16:34:38 +02:00
Martin Povišer
adc1a01490
select: Refactor some flag validation
2024-05-21 16:29:20 +02:00
Martin Povišer
c0a196173a
Rename `bbox_derive` to `box_derive`
2024-05-21 16:18:03 +02:00
N. Engelhardt
e940d248c0
Merge pull request #4326 from povik/logcmd
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Extend `log` command with `-push`, `-pop`, `-header` options
2024-05-21 15:22:40 +02:00
Martin Povišer
5c929a91c2
bbox_derive: Write help
2024-05-21 14:57:37 +02:00
Martin Povišer
88af059fad
bbox_derive: Fix `done` base type confusion
2024-05-21 14:57:26 +02:00
Emil J. Tywoniak
44b0fdc2bf
bbox_derive: add assert and debug print
2024-05-03 20:43:01 +02:00
Emil J. Tywoniak
e8c58a5528
bbox_derive: fix unininitialized memory UB when run with no named args
2024-05-03 20:41:42 +02:00
Martin Povišer
4c000d3aba
Add new `bbox_derive` command for blackbox derivation
2024-05-03 20:39:11 +02:00
Emil J. Tywoniak
e939182e68
cellmatch: add comments
2024-05-03 16:42:41 +02:00
Martin Povišer
b143e5678f
cellmatch: Rename the special design to `$cellmatch`
2024-05-03 16:42:41 +02:00
Martin Povišer
c0e68dcc4d
cellmatch: Add debug print
2024-05-03 16:42:41 +02:00
Martin Povišer
6a9858cdad
cellmatch: Delegate evaluation to `ConstEval`
2024-05-03 16:42:41 +02:00
Martin Povišer
86e1080f05
cellmatch: New pass
2024-05-03 16:42:41 +02:00
Martin Povišer
6ff4ecb2b4
techmap: Remove `techmap_chtype` from the result
2024-05-03 13:33:28 +02:00
Martin Povišer
fc82251105
techmap: Support dynamic cell types
2024-05-03 13:33:28 +02:00
N. Engelhardt
34d9a7451e
Merge pull request #4333 from YosysHQ/fix_hierarchy_generate
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fix hierarchy -generate mode handling of cells
2024-04-25 09:56:24 +02:00
KrystalDelusion
c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup
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Typo fixing
2024-04-25 09:54:48 +12:00
Martin Povišer
171577f909
Merge pull request #4340 from gadfort/abc-lib-merge
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add support for using ABCs library merging when providing multiple liberty files
2024-04-17 22:01:20 +02:00
Jannis Harder
2bd889a59a
formalff -setundef: Fix handling for has_srst FFs
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The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to
a copy and paste error.
This would crash when `has_ce` was false and could incorrectly determine
that an initial value is unused when `has_ce` and `has_srst` are both
set.
2024-04-15 11:53:30 +02:00
Martin Povišer
b827b9862f
Merge pull request #4265 from povik/iattr_help
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memory_map: Explain `-iattr` better
2024-04-13 18:13:58 +02:00
Martin Povišer
4a8cdfabbb
Merge pull request #4169 from povik/clean-opt_clean-step2
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opt_clean: Remove dead assertion
2024-04-13 18:12:40 +02:00
Peter Gadfort
a48825a604
add support for using ABCs library merging when providing multiple liberty files
2024-04-12 13:57:29 -04:00
N. Engelhardt
b87327d1b9
fix hierarchy -generate mode handling of cells
2024-04-12 13:38:33 +02:00
Emil J
c5912f4f95
Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning
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opt_demorgan: fix extra args warning
2024-04-10 12:49:14 +02:00
Martin Povišer
b00abe4a26
Extend `log` command with `-push`, `-pop`, `-header` options
2024-04-10 11:49:20 +02:00
Martin Povišer
47931f9050
Merge pull request #4295 from gadfort/add-ports-stat
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add port statistics to stat command
2024-04-08 11:12:02 +02:00
Emil J. Tywoniak
4bb3b099d2
opt_demorgan: fix extra args warning
2024-04-03 10:02:53 +02:00
N. Engelhardt
c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges
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Use cell edges data in `check`, improve messages
2024-03-25 16:19:35 +01:00
Peter Gadfort
160e3e089a
add port statistics to stat command
2024-03-22 09:20:20 -04:00
Krystine Sherwin
3eeefd23e3
Typo fixup(s)
2024-03-18 11:09:23 +13:00
N. Engelhardt
e4f11eb0a0
Merge pull request #4228 from povik/synth-inject
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synth: Introduce `-extra-map` for amending techmap
2024-03-11 14:55:45 +01:00
Martin Povišer
206d894c56
check: Omit private wires in loop report
2024-03-11 10:45:36 +01:00
Martin Povišer
d01728aaa5
celledges: Register async FF paths
2024-03-11 10:45:36 +01:00
Martin Povišer
4fdcf388d3
check: Assert edges data is not out-of-bounds
2024-03-11 10:45:17 +01:00
Martin Povišer
b6112b3551
check: Consider read ports in loop detection
2024-03-11 10:45:17 +01:00
Martin Povišer
fa74d0bd1a
check: Use cell edges data in detecting combinational loops
2024-03-11 10:43:49 +01:00
Martin Povišer
c5ae74af34
check: Improve found loop logging
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Print the detected loop in-order, and include source location for each
node, if available.
2024-03-11 10:43:49 +01:00
N. Engelhardt
d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
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celledges: support shift ops
2024-03-08 09:35:47 +01:00
Martin Povišer
158fbf881e
memory_map: Explain `-iattr` better
2024-03-06 15:15:37 +01:00
Jannis Harder
04ecabdd1f
Merge pull request #4222 from jix/pdr-X
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write_aiger: Include `$assert` and `$assume` cells in -ywmap output
2024-03-05 15:13:51 +01:00
Jannis Harder
d8cdc213a6
rename -witness: Bug fix and rename formal cells
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Rename formal cells in addition to witness signals. This is required to
reliably track individual property states for the non-smtbmc flows.
Also removes a misplced `break` which resulted in only partial witness
renaming.
2024-03-04 16:53:03 +01:00
Jannis Harder
16f6386613
Merge pull request #4224 from povik/equiv_simple-fix
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equiv_simple: Take FFs into account for driver map
2024-03-04 15:53:34 +01:00
N. Engelhardt
6dc5da3ed9
Merge pull request #4232 from povik/mem-ui-fixes
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opt_mem, memory_*: Refuse to operate in presence of processes
2024-02-26 16:09:27 +01:00
Roland Coeurjoly
4a2fb18718
Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc
2024-02-25 17:23:56 +01:00
Roland Coeurjoly
033fa10307
We use CXX instead of LD for linking yosys-filterlib
2024-02-25 16:49:28 +01:00
Martin Povišer
030d639201
opt_mem, memory_*: Refuse to operate in presence of processes
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Processes can contain `MemWriteAction` entries which are invisible to
most passes operating on memories but which will be lowered to write
ports later on by `proc_memwr`. For that reason we can get corrupted
RTLIL if we sequence the memory passes before `proc`. Address that by
making the affected memory passes ignore modules with processes.
2024-02-23 12:27:53 +01:00
Martin Povišer
975517b022
memory_memx: Fix log header
2024-02-23 12:27:10 +01:00
Martin Povišer
53ca7b48f8
techmap: Fix help message wording
2024-02-22 22:00:56 +01:00
Martin Povišer
4c96546717
equiv_simple: Take FFs into account for driver map
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This fixes an issue introduced in commit 26644ea
due to which flip-flops
are inadvertently ignored when building up driver map. The mentioned
commit wasn't without functional change after all.
2024-02-21 12:05:52 +01:00
Austin Rovinski
03cadf6474
dfflibmap: use patmatch() from kernel/yosys.cc
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Replace OS matching functions with yosys kernel function
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-20 11:04:55 -05:00
Miodrag Milanović
bc8a3a5b18
Merge pull request #4219 from rovinski/master
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dfflibmap: Add a -dont_use flag to ignore cells
2024-02-20 12:43:44 +01:00
Miodrag Milanović
a3c81f4d62
Merge pull request #4216 from YosysHQ/show_href
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show: Add option to add cell/wire "src" attribute into graphviz attribute href
2024-02-19 20:50:53 +01:00
Austin Rovinski
5059bb1d4f
dfflibmap: force PathMatchSpecA on WIN32
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Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or
LPCWSTR argument. char* is only convertable to LPCSTR, so use that
implementation
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-19 14:40:46 -05:00
Austin Rovinski
689feed012
dfflibmap: Add a -dont_use flag to ignore cells
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This is an alternative to setting the dont_use property in lib. This brings
dfflibmap in parity with the abc pass for dont_use.
Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-19 13:00:18 -05:00
Martin Povišer
db947e4c71
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch
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proc_rom: don't assert on big actionless switch.
2024-02-19 16:21:40 +01:00
N. Engelhardt
4b99db0b73
Merge pull request #4177 from povik/connect-extra_args
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connect: Do interpret selection arguments
2024-02-19 15:18:37 +01:00
N. Engelhardt
aebb7a0c4d
Merge pull request #4188 from povik/dlatch-bwmux
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proc_dlatch: Include `$bwmux` among considered mux cells
2024-02-19 15:15:03 +01:00
Amelia Cuss
bf4a46ccb3
proc_rom: don't assert on big actionless switch.
...
See the test case. PROC_ROM will consider this for evaluation, even
though -- without any actions -- lhs is empty (but still "uniform").
A zero-width memory is constructed, which later fails check with:
ERROR: Assert `width != 0' failed in kernel/mem.cc:518.
Ensure we don't proceed if there's nothing to encode.
2024-02-18 01:33:28 +11:00
N. Engelhardt
61b3b9b58a
Merge pull request #4197 from QuantamHD/sequential_area
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stat: Add sequential area output to stat -liberty
2024-02-16 19:15:44 +01:00
Ethan Mahintorabi
b8a1009de9
Update passes/cmds/stat.cc
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Make reporting line more clear about the non cumulative area of sequential cells
Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
2024-02-16 07:44:09 -08:00
Ethan Mahintorabi
f0df0e3912
update type and variable names
...
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-16 00:01:44 +00:00
Ethan Mahintorabi
2d8343d423
update type and variable names
...
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-15 23:59:19 +00:00
Jannis Harder
bbdfcfdf30
clk2fflogic: Fix handling of $check cells
...
Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.
Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
2024-02-14 11:42:27 +01:00
Miodrag Milanovic
834276a2f7
show: Add option to add cell/wire "src" attribute into graphviz attribute href
2024-02-14 09:50:53 +01:00
Miodrag Milanović
edb95c69a9
Merge pull request #4084 from jix/scopeinfo
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$scopeinfo support
2024-02-12 09:51:22 +01:00
Ethan Mahintorabi
8566489d85
stat: Add sequential area output to stat -liberty
...
Checks to see if a cell is of type ff in the liberty,
and keeps track of an additional area value.
```
Chip area for module '\addr': 92.280720
Sequential area for module '\addr': 38.814720
```
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-09 23:51:00 +00:00
Miodrag Milanović
2f4c917dac
Merge pull request #4181 from povik/ci-cxxstd-fix
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ci: Fix CXXSTD typo
2024-02-08 18:55:47 +01:00
Martin Povišer
043f1e2bcb
opt_lut: Remove leftover `-dlogic` help
2024-02-08 17:49:44 +01:00
Martin Povišer
af1a5cfeb9
Address `SigBit`/`SigSpec` confusion issues under c++20
2024-02-08 17:48:36 +01:00
Martin Povišer
862f2fd705
proc_dlatch: Include `$bwmux` among considered mux cells
2024-02-08 00:08:50 +01:00
Jannis Harder
bfd9cf63db
Ignore $scopeinfo in opt_merge
2024-02-06 17:51:29 +01:00
Jannis Harder
8902fc94b6
Suport $scopeinfo in flatten and opt_clean
2024-02-06 17:51:29 +01:00
Miodrag Milanović
269c50f90e
Merge pull request #4130 from jix/hierarchy-defer-notop
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hierarchy: Without a known top module, derive all deferred modules
2024-02-06 12:08:01 +01:00
Jannis Harder
0470cbb00d
hierarchy: Without a known top module, derive all deferred modules
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This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
2024-02-06 10:31:40 +01:00
Claire Xen
1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite
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Add API to overwrite existing pass from plugin
2024-02-05 23:49:24 +01:00
N. Engelhardt
f96e27ac14
Merge pull request #4123 from povik/clean-opt_clean
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opt_clean: Add commentary, remove dead code
2024-02-05 15:08:34 +01:00
Catherine
c7bf0e3b8f
Add new `$check` cell to represent assertions with a message.
2024-02-01 20:10:39 +01:00
Jannis Harder
e1a59ba80b
async2sync, clk2fflogic: Add support for $check and $print cells
2024-02-01 20:10:39 +01:00
Jannis Harder
6c4902313b
chformal: Support $check cells and add chformal -lower
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This adds support for `$check` cells in chformal and adds a `-lower`
mode which converts `$check` cells into `$assert` etc. cells with a
`$print` cell to output the `$check` message.
2024-02-01 20:10:39 +01:00
Martin Povišer
a84fa0a277
connect: Do interpret selection arguments
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Instead of silently ignoring what would ordinarily be the selection
arguments to a pass, interpret those and mark the support in the help
message.
2024-02-01 10:28:36 +01:00
Martin Povišer
6c4bc5aae5
Merge pull request #4165 from phsauter/shiftadd-offset-fix
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peepopt: handle offset too large in `shiftadd`
2024-01-31 13:47:39 +01:00
Philippe Sauter
cbdf9b2f9c
peepopt: handle empty src-attribute in shiftadd
2024-01-31 13:07:01 +01:00
Claire Xenia Wolf
4fa314c0bd
Add API to overwrite existing pass from plugin
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-01-30 17:51:11 +01:00
Philippe Sauter
7f8b6dd982
peepopt: delete unnecessary comment in shiftadd
2024-01-30 09:51:21 +01:00
Martin Povišer
23c9828d70
opt_clean: Remove dead branch
2024-01-29 11:26:44 +01:00
Martin Povišer
7afc0696e2
opt_clean: Assert an impossible path isn't taken
2024-01-29 11:26:44 +01:00
Martin Povišer
ec065186d3
opt_clean: Add commentary around wire cleaning, NFC
2024-01-29 11:26:44 +01:00
Philippe Sauter
68a9aa7c29
peepopt: handle offset too large in `shiftadd`
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If the offset is larger than the signal itself,
meaning the signal is completely shifted out,
it tried to extract a negative amount of bits from the old signal.
This RTL pattern is suspicious since it is a complicated way of
arriving at a constant value, so we warn the user.
2024-01-26 16:44:30 +01:00
Jannis Harder
7c818d30f7
sim: Bring $print trigger/sampling semantics in line with FFs
2024-01-25 16:21:03 +01:00
Catherine
3d9e44d182
hierarchy: keep display statements, like formal assertions.
2024-01-22 10:09:22 +00:00
Stephen Tong
b3e7390c0e
Fix typo in stat help
2024-01-21 16:32:05 -05:00
N. Engelhardt
e1f4c5c9cb
Merge pull request #4133 from YosysHQ/show_color_proc
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show: allow setting colors via selection on PROC boxes
2024-01-17 17:56:53 +01:00
Martin Povišer
6a7fad4dd9
Merge pull request #4132 from povik/opt_lut_ice40
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opt_lut: Replace `-dlogic` with `-tech ice40`
2024-01-17 14:26:28 +01:00