mirror of https://github.com/YosysHQ/yosys.git
update type and variable names
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
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2d8343d423
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@ -28,9 +28,9 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct cell_data_t {
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struct cell_area_t {
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double area;
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bool is_flip_flop;
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bool is_sequential;
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};
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struct statdata_t
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@ -80,7 +80,7 @@ struct statdata_t
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#undef X
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}
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statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_data_t> &cell_properties, string techname)
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statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_properties, string techname)
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{
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tech = techname;
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@ -139,8 +139,8 @@ struct statdata_t
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if (!cell_properties.empty()) {
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if (cell_properties.count(cell_type)) {
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cell_data_t cell_data = cell_properties.at(cell_type);
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if (cell_data.is_flip_flop) {
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cell_area_t cell_data = cell_properties.at(cell_type);
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if (cell_data.is_sequential) {
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sequential_area += cell_data.area;
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}
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area += cell_data.area;
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@ -338,7 +338,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
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return mod_data;
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}
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void read_liberty_cellarea(dict<IdString, cell_data_t> &cell_properties, string liberty_file)
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void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_properties, string liberty_file)
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{
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std::ifstream f;
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f.open(liberty_file.c_str());
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@ -397,7 +397,7 @@ struct StatPass : public Pass {
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bool width_mode = false, json_mode = false;
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RTLIL::Module *top_mod = nullptr;
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std::map<RTLIL::IdString, statdata_t> mod_stat;
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dict<IdString, cell_data_t> cell_properties;
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dict<IdString, cell_area_t> cell_properties;
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string techname;
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size_t argidx;
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