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Typo fixup(s)

This commit is contained in:
Krystine Sherwin 2024-03-18 11:08:13 +13:00
parent 3231c1cd93
commit 3eeefd23e3
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3 changed files with 3 additions and 3 deletions
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2
frontends/ast/genrtlil.cc
View File

@ -2224,7 +2224,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
else
input_error("FATAL.\n");
} else {
input_error("Unknown elabortoon system task '%s'.\n", str.c_str());
input_error("Unknown elaboration system task '%s'.\n", str.c_str());
}
} break;

2
kernel/driver.cc
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@ -356,7 +356,7 @@ int main(int argc, char **argv)
printf(" -V\n");
printf(" print version information and exit\n");
printf("\n");
printf("The option -S is an shortcut for calling the \"synth\" command, a default\n");
printf("The option -S is a shortcut for calling the \"synth\" command, a default\n");
printf("script for transforming the Verilog input to a gate-level netlist. For example:\n");
printf("\n");
printf(" yosys -o output.blif -S input.v\n");

2
passes/pmgen/ice40_dsp.cc
View File

@ -289,7 +289,7 @@ struct Ice40DspPass : public Pass {
log("\n");
log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n");
log("optional hold), and post-adder into into the SB_MAC16 resource.\n");
log("optional hold), and post-adder into the SB_MAC16 resource.\n");
log("\n");
log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
log("input will be folded into the DSP. In this scenario only, resetting the\n");