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replace space indent with tab indent

This commit is contained in:
Chun Lin Min 2024-07-02 13:47:18 -07:00
parent acddc36389
commit 2ced2752e9
31 changed files with 791 additions and 797 deletions
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38
passes/pmgen/mchp_dsp_CREG.pmg
View File

@ -56,7 +56,7 @@ udata <Cell*> dff
// and (b) uses the 'C' port
match dsp
select dsp->type.in(\MACC_PA)
select port(dsp, \C_BYPASS, SigSpec()).is_fully_ones()
select port(dsp, \C_BYPASS, SigSpec()).is_fully_ones()
select nusers(port(dsp, \C, SigSpec())) > 1
endmatch
@ -76,14 +76,14 @@ code sigC sigP clock
SigSpec P = port(dsp, \P);
// Only care about those bits that are used
int i;
for (i = GetSize(P)-1; i >= 0; i--)
if (nusers(P[i]) > 1)
break;
i++;
log_assert(nusers(P.extract_end(i)) <= 1);
sigP = P.extract(0, i);
// Only care about those bits that are used
int i;
for (i = GetSize(P)-1; i >= 0; i--)
if (nusers(P[i]) > 1)
break;
i++;
log_assert(nusers(P.extract_end(i)) <= 1);
sigP = P.extract(0, i);
clock = port(dsp, \CLK, SigBit());
endcode
@ -150,20 +150,20 @@ match ff
endmatch
code argQ
// Check that reset value, if present, is fully 0.
// Check that reset value, if present, is fully 0.
bool noResetFlop = ff->type.in($dff, $dffe);
bool srstZero = ff->type.in($sdff, $sdffe) && param(ff, \SRST_VALUE).is_fully_zero();
bool arstZero = ff->type.in($adff, $adffe) && param(ff, \ARST_VALUE).is_fully_zero();
bool resetLegal = noResetFlop || srstZero || arstZero;
if (resetLegal)
{
SigSpec Q = port(ff, \Q);
dff = ff;
dffclock = port(ff, \CLK);
dffD = argQ;
SigSpec D = port(ff, \D);
argQ = Q;
dffD.replace(argQ, D);
}
{
SigSpec Q = port(ff, \Q);
dff = ff;
dffclock = port(ff, \CLK);
dffD = argQ;
SigSpec D = port(ff, \D);
argQ = Q;
dffD.replace(argQ, D);
}
endcode

150
passes/pmgen/mchp_dsp_cascade.pmg
View File

@ -60,16 +60,16 @@ endcode
// Helper function to remove unused bits
code
unextend = [](const SigSpec &sig) {
int i;
for (i = GetSize(sig)-1; i > 0; i--)
if (sig[i] != sig[i-1])
break;
// Do not remove non-const sign bit
if (sig[i].wire)
++i;
return sig.extract(0, i);
};
unextend = [](const SigSpec &sig) {
int i;
for (i = GetSize(sig)-1; i > 0; i--)
if (sig[i] != sig[i-1])
break;
// Do not remove non-const sign bit
if (sig[i].wire)
++i;
return sig.extract(0, i);
};
endcode
// (1) Starting from a DSP cell that
@ -85,57 +85,57 @@ endmatch
// height of a DSP column) with each DSP in each chunk being rewritten
// to use [ABP]COUT -> [ABP]CIN cascading as appropriate
code
visited.clear();
visited.insert(first);
visited.clear();
visited.insert(first);
longest_chain.clear();
chain.emplace_back(first, -1);
subpattern(tail);
finally
// longest cascade chain has been found with DSP "first" being the head of the chain
// do some post processing
// longest cascade chain has been found with DSP "first" being the head of the chain
// do some post processing
chain.pop_back();
visited.clear();
visited.clear();
log_assert(chain.empty());
if (GetSize(longest_chain) > 1) {
Cell *dsp = std::get<0>(longest_chain.front());
Cell *dsp_pcin;
int SHIFT = -1;
int SHIFT = -1;
for (int i = 1; i < GetSize(longest_chain); i++) {
log_assert(dsp->type.in(\MACC_PA));
log_assert(dsp->type.in(\MACC_PA));
std::tie(dsp_pcin,SHIFT) = longest_chain[i];
std::tie(dsp_pcin,SHIFT) = longest_chain[i];
// Chain length exceeds the maximum cascade length, must split it up
// Chain length exceeds the maximum cascade length, must split it up
if (i % MAX_DSP_CASCADE > 0) {
Wire *cascade = module->addWire(NEW_ID, 48);
Wire *cascade = module->addWire(NEW_ID, 48);
// zero port C and move wire to cascade
dsp_pcin->setPort(ID(C), Const(0, 48));
dsp_pcin->setPort(ID(CDIN), cascade);
dsp->setPort(ID(CDOUT), cascade);
// zero port C and move wire to cascade
dsp_pcin->setPort(ID(C), Const(0, 48));
dsp_pcin->setPort(ID(CDIN), cascade);
dsp->setPort(ID(CDOUT), cascade);
// Configure wire to cascade the dsps
add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp);
// Configure wire to cascade the dsps
add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp);
// configure mux to use cascade for signal E
SigSpec cdin_fdbk_sel = port(dsp_pcin, \CDIN_FDBK_SEL, Const(0, 2));
cdin_fdbk_sel[1] = State::S1;
dsp_pcin->setPort(\CDIN_FDBK_SEL, cdin_fdbk_sel);
// configure mux to use cascade for signal E
SigSpec cdin_fdbk_sel = port(dsp_pcin, \CDIN_FDBK_SEL, Const(0, 2));
cdin_fdbk_sel[1] = State::S1;
dsp_pcin->setPort(\CDIN_FDBK_SEL, cdin_fdbk_sel);
// check if shifting is required for wide multiplier implmentation
if (SHIFT == 17)
{
dsp_pcin->setPort(\ARSHFT17, State::S1);
}
// check if shifting is required for wide multiplier implmentation
if (SHIFT == 17)
{
dsp_pcin->setPort(\ARSHFT17, State::S1);
}
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
} else {
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
@ -159,47 +159,47 @@ arg next
// (b) 'C' port is driven by the 'P' output of the previous DSP cell
// (c) has its 'PCIN' port unused
match nextP
// find candidates where nextP.C port is driven (maybe partially) by chain's tail DSP.P port
// and with no registers in between (since cascade path cannot be pipelined)
// find candidates where nextP.C port is driven (maybe partially) by chain's tail DSP.P port
// and with no registers in between (since cascade path cannot be pipelined)
// reg C must not be used
select port(nextP, \C_BYPASS, SigSpec()).is_fully_ones()
// reg C must not be used
select port(nextP, \C_BYPASS, SigSpec()).is_fully_ones()
// must be same DSP type
select nextP->type.in(\MACC_PA)
// must be same DSP type
select nextP->type.in(\MACC_PA)
// port C should be driven by something
// port C should be driven by something
select nusers(port(nextP, \C, SigSpec())) > 1
// CIN must be unused
// CIN must be unused
select nusers(port(nextP, \PCIN, SigSpec())) == 0
// should not have internal feedback connection
select port(nextP, \CDIN_FDBK_SEL, SigSpec()).is_fully_zero()
// SHIFT should be unused
select port(nextP, \ARSHFT17_BYPASS).is_fully_ones()
select port(nextP, \ARSHFT17).is_fully_zero()
select nusers(port(nextP, \ARSHFT17, SigSpec())) == 0
// should not have internal feedback connection
select port(nextP, \CDIN_FDBK_SEL, SigSpec()).is_fully_zero()
// current DSP cell can be cascaded with the back of the cascade chain
// SHIFT should be unused
select port(nextP, \ARSHFT17_BYPASS).is_fully_ones()
select port(nextP, \ARSHFT17).is_fully_zero()
select nusers(port(nextP, \ARSHFT17, SigSpec())) == 0
// current DSP cell can be cascaded with the back of the cascade chain
// index <SigBit> port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[17]
filter port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[17]
filter port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[17]
// semioptional
optional
optional
endmatch
code next
next = nextP;
// keep DSP type consistent in the chain
// currently since we only have one type anyways, this line is always false
// keep DSP type consistent in the chain
// currently since we only have one type anyways, this line is always false
if (next && next->type != first->type) reject;
// break infinite recursion when there's a combinational loop
if (visited.count(next) > 0) reject;
// break infinite recursion when there's a combinational loop
if (visited.count(next) > 0) reject;
endcode
@ -207,32 +207,30 @@ endcode
// longest possible chain
code
if (next) {
SigSpec driver_sigP = port(std::get<0>(chain.back()), \P);
int shift = 0;
if (port(next, \C)[0] == port(std::get<0>(chain.back()), \P)[17]) shift = 17;
SigSpec driver_sigP = port(std::get<0>(chain.back()), \P);
int shift = 0;
if (port(next, \C)[0] == port(std::get<0>(chain.back()), \P)[17]) shift = 17;
chain.emplace_back(next, shift);
visited.insert(next);
visited.insert(next);
SigSpec sigC = unextend(port(next, \C));
// Make sure driverDSP.P === DSP.C
if (GetSize(sigC) + shift <= GetSize(driver_sigP) && driver_sigP.extract(shift, GetSize(sigC)) == sigC)
{
subpattern(tail);
}
// Make sure driverDSP.P === DSP.C
if (GetSize(sigC) + shift <= GetSize(driver_sigP) && driver_sigP.extract(shift, GetSize(sigC)) == sigC)
{
subpattern(tail);
}
} else {
if (GetSize(chain) > GetSize(longest_chain))
longest_chain = chain;
}
finally
if (next)
{
visited.erase(next);
chain.pop_back();
}
{
visited.erase(next);
chain.pop_back();
}
endcode

30
techlibs/mchp/LSRAM.txt
View File

@ -45,11 +45,11 @@ ram block $__LSRAM_TDP_ {
option "WIDTH_CONFIG" "REGULAR" {
# Data-Width | Address bits
# 1 | 14
# 2 | 13
# 1 | 14
# 2 | 13
# 4 | 12
# 8 | 11
# 16 | 10
# 16 | 10
# 14 address bits
abits 14;
@ -60,12 +60,12 @@ ram block $__LSRAM_TDP_ {
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width | Address bits
# 5 | 12
# 10 | 11
# 20 | 10
# 5 | 12
# 10 | 11
# 20 | 10
# Quick "hack" to fix address bit alignment by setting address bits to 12.
# If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20
# If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20
# THe LSRAM_map.v file detects if this option is being used, and adjusts the address port alignments accordingly.
abits 12;
@ -134,12 +134,12 @@ ram block $__LSRAM_SDP_ {
option "WIDTH_CONFIG" "REGULAR" {
# Data-Width | Address bits
# 1 | 14
# 2 | 13
# 1 | 14
# 2 | 13
# 4 | 12
# 8 | 11
# 16 | 10
# 32 | 9
# 16 | 10
# 32 | 9
abits 14;
@ -152,10 +152,10 @@ ram block $__LSRAM_SDP_ {
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width | Address bits
# 5 | 12
# 10 | 11
# 20 | 10
# 40 | 9
# 5 | 12
# 10 | 11
# 20 | 10
# 40 | 9
# Same trick as TSP RAM for alignment
abits 12;

303
techlibs/mchp/LSRAM_map.v
View File

@ -73,25 +73,25 @@ wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 :
// wires for write data
generate
wire [19:0] A_write_data;
wire [19:0] B_write_data;
if (PORT_A_WIDTH == 16) begin
assign A_write_data[7:0] = PORT_A_WR_DATA[7:0];
assign A_write_data[17:10] = PORT_A_WR_DATA[15:8];
assign A_write_data[9:8] = 2'b0;
assign A_write_data[19:18] = 2'b0;
end else begin
assign A_write_data[PORT_A_WIDTH-1:0] = PORT_A_WR_DATA;
end
wire [19:0] A_write_data;
wire [19:0] B_write_data;
if (PORT_A_WIDTH == 16) begin
assign A_write_data[7:0] = PORT_A_WR_DATA[7:0];
assign A_write_data[17:10] = PORT_A_WR_DATA[15:8];
assign A_write_data[9:8] = 2'b0;
assign A_write_data[19:18] = 2'b0;
end else begin
assign A_write_data[PORT_A_WIDTH-1:0] = PORT_A_WR_DATA;
end
if (PORT_B_WIDTH == 16) begin
assign B_write_data[7:0] = PORT_B_WR_DATA[7:0];
assign B_write_data[17:10] = PORT_B_WR_DATA[15:8];
assign B_write_data[9:8] = 2'b0;
assign B_write_data[19:18] = 2'b0;
end else begin
assign B_write_data[PORT_B_WIDTH-1:0] = PORT_B_WR_DATA;
end
if (PORT_B_WIDTH == 16) begin
assign B_write_data[7:0] = PORT_B_WR_DATA[7:0];
assign B_write_data[17:10] = PORT_B_WR_DATA[15:8];
assign B_write_data[9:8] = 2'b0;
assign B_write_data[19:18] = 2'b0;
end else begin
assign B_write_data[PORT_B_WIDTH-1:0] = PORT_B_WR_DATA;
end
endgenerate
// wires for read data
@ -106,58 +106,58 @@ wire [1:0] B_write_EN = (PORT_B_WR_EN_WIDTH == 1) ? {1'b0, PORT_B_WR_EN} : PORT_
// port width
wire [2:0] A_width = (PORT_A_WIDTH == 1) ? 3'b000 :
(PORT_A_WIDTH == 2) ? 3'b001 :
(PORT_A_WIDTH == 4 || PORT_A_WIDTH == 5) ? 3'b010 :
(PORT_A_WIDTH == 8 || PORT_A_WIDTH == 10) ? 3'b011 : 3'b100;
(PORT_A_WIDTH == 2) ? 3'b001 :
(PORT_A_WIDTH == 4 || PORT_A_WIDTH == 5) ? 3'b010 :
(PORT_A_WIDTH == 8 || PORT_A_WIDTH == 10) ? 3'b011 : 3'b100;
wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 :
(PORT_B_WIDTH == 2) ? 3'b001 :
(PORT_B_WIDTH == 4 || PORT_B_WIDTH == 5) ? 3'b010 :
(PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
(PORT_B_WIDTH == 2) ? 3'b001 :
(PORT_B_WIDTH == 4 || PORT_B_WIDTH == 5) ? 3'b010 :
(PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
// write modes
wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
RAM1K20 #(
`PARAMS_INIT_LSRAM
`PARAMS_INIT_LSRAM
) _TECHMAP_REPLACE_ (
// port A
.A_ADDR(A_address),
.A_BLK_EN(A_BLK_SEL),
.A_CLK(PORT_A_CLK),
.A_DIN(A_write_data),
.A_DOUT(A_read_data),
.A_WEN(A_write_EN),
.A_REN(PORT_A_RD_EN),
.A_WIDTH(A_width),
.A_WMODE(A_write_mode),
.A_BYPASS(1'b1),
.A_DOUT_EN(1'b1),
.A_DOUT_SRST_N(1'b1),
.A_DOUT_ARST_N(1'b1),
// port B
.B_ADDR(B_address),
.B_BLK_EN(B_BLK_SEL),
.B_CLK(PORT_B_CLK),
.B_DIN(B_write_data),
.B_DOUT(B_read_data),
.B_WEN(B_write_EN),
.B_REN(PORT_B_RD_EN),
.B_WIDTH(B_width),
.B_WMODE(B_write_mode),
.B_BYPASS(1'b1),
.B_DOUT_EN(1'b1),
.B_DOUT_SRST_N(1'b1),
.B_DOUT_ARST_N(1'b1),
// Disable ECC for TDP
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
// port A
.A_ADDR(A_address),
.A_BLK_EN(A_BLK_SEL),
.A_CLK(PORT_A_CLK),
.A_DIN(A_write_data),
.A_DOUT(A_read_data),
.A_WEN(A_write_EN),
.A_REN(PORT_A_RD_EN),
.A_WIDTH(A_width),
.A_WMODE(A_write_mode),
.A_BYPASS(1'b1),
.A_DOUT_EN(1'b1),
.A_DOUT_SRST_N(1'b1),
.A_DOUT_ARST_N(1'b1),
// port B
.B_ADDR(B_address),
.B_BLK_EN(B_BLK_SEL),
.B_CLK(PORT_B_CLK),
.B_DIN(B_write_data),
.B_DOUT(B_read_data),
.B_WEN(B_write_EN),
.B_REN(PORT_B_RD_EN),
.B_WIDTH(B_width),
.B_WMODE(B_write_mode),
.B_BYPASS(1'b1),
.B_DOUT_EN(1'b1),
.B_DOUT_SRST_N(1'b1),
.B_DOUT_ARST_N(1'b1),
// Disable ECC for TDP
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
);
@ -201,122 +201,119 @@ assign B_address = (OPTION_WIDTH_CONFIG == "REGULAR") ? PORT_W_ADDR : {PORT_W_AD
// port A is for read, port B for write
parameter PORT_W_USED = 0;
parameter PORT_R_USED = 0;
wire [2:0] A_BLK_SEL = (PORT_R_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] B_BLK_SEL = (PORT_W_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] A_BLK_SEL = (PORT_R_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] B_BLK_SEL = (PORT_W_USED == 1) ? 3'b111 : 3'b000;
// read/write data & write enables
// Currently support only wide write, width = {32, 40}
generate
wire [19:0] A_write_data;
wire [19:0] B_write_data;
wire [1:0] A_write_EN;
wire [1:0] B_write_EN;
wire [19:0] A_write_data;
wire [19:0] B_write_data;
wire [1:0] A_write_EN;
wire [1:0] B_write_EN;
// write port (A provides MSB)
if (PORT_W_WIDTH == 32) begin
// write port (A provides MSB)
if (PORT_W_WIDTH == 32) begin
assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
assign B_write_data[8:5] = PORT_W_WR_DATA[7:4];
assign B_write_data[13:10] = PORT_W_WR_DATA[11:8];
assign B_write_data[18:15] = PORT_W_WR_DATA[15:12];
assign B_write_data[4] = 1'b0;
assign B_write_data[9] = 1'b0;
assign B_write_data[14] = 1'b0;
assign B_write_data[19] = 1'b0;
assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
assign B_write_data[8:5] = PORT_W_WR_DATA[7:4];
assign B_write_data[13:10] = PORT_W_WR_DATA[11:8];
assign B_write_data[18:15] = PORT_W_WR_DATA[15:12];
assign B_write_data[4] = 1'b0;
assign B_write_data[9] = 1'b0;
assign B_write_data[14] = 1'b0;
assign B_write_data[19] = 1'b0;
assign A_write_data[3:0] = PORT_W_WR_DATA[19:16];
assign A_write_data[8:5] = PORT_W_WR_DATA[23:20];
assign A_write_data[13:10] = PORT_W_WR_DATA[27:24];
assign A_write_data[18:15] = PORT_W_WR_DATA[31:28];
assign A_write_data[4] = 1'b0;
assign A_write_data[9] = 1'b0;
assign A_write_data[14] = 1'b0;
assign A_write_data[19] = 1'b0;
end else if (PORT_W_WIDTH == 40) begin
assign B_write_data = PORT_W_WR_DATA[19:0];
assign A_write_data = PORT_W_WR_DATA[39:20];
end
assign A_write_data[3:0] = PORT_W_WR_DATA[19:16];
assign A_write_data[8:5] = PORT_W_WR_DATA[23:20];
assign A_write_data[13:10] = PORT_W_WR_DATA[27:24];
assign A_write_data[18:15] = PORT_W_WR_DATA[31:28];
assign A_write_data[4] = 1'b0;
assign A_write_data[9] = 1'b0;
assign A_write_data[14] = 1'b0;
assign A_write_data[19] = 1'b0;
end else if (PORT_W_WIDTH == 40) begin
assign B_write_data = PORT_W_WR_DATA[19:0];
assign A_write_data = PORT_W_WR_DATA[39:20];
end
// byte-write enables
assign A_write_EN = PORT_W_WR_EN[1:0];
assign B_write_EN = PORT_W_WR_EN[3:2];
// byte-write enables
assign A_write_EN = PORT_W_WR_EN[1:0];
assign B_write_EN = PORT_W_WR_EN[3:2];
// read ports (A provides MSB)
wire [19:0] A_read_data;
wire [19:0] B_read_data;
if (PORT_R_WIDTH == 32) begin
assign PORT_R_RD_DATA[3:0] = B_read_data[3:0];
assign PORT_R_RD_DATA[8:5] = B_read_data[7:4];
assign PORT_R_RD_DATA[13:10] = B_read_data[11:8];
assign PORT_R_RD_DATA[18:15] = B_read_data[15:12];
// read ports (A provides MSB)
wire [19:0] A_read_data;
wire [19:0] B_read_data;
if (PORT_R_WIDTH == 32) begin
assign PORT_R_RD_DATA[3:0] = B_read_data[3:0];
assign PORT_R_RD_DATA[8:5] = B_read_data[7:4];
assign PORT_R_RD_DATA[13:10] = B_read_data[11:8];
assign PORT_R_RD_DATA[18:15] = B_read_data[15:12];
assign PORT_R_RD_DATA[19:16] = A_read_data[3:0];
assign PORT_R_RD_DATA[23:20] = A_read_data[8:5];
assign PORT_R_RD_DATA[27:24] = A_read_data[13:10];
assign PORT_R_RD_DATA[31:28] = A_read_data[18:15];
end else if (PORT_R_WIDTH == 40) begin
assign PORT_R_RD_DATA[19:0] = B_read_data[19:0];
assign PORT_R_RD_DATA[39:20] = A_read_data[19:0];
end
assign PORT_R_RD_DATA[19:16] = A_read_data[3:0];
assign PORT_R_RD_DATA[23:20] = A_read_data[8:5];
assign PORT_R_RD_DATA[27:24] = A_read_data[13:10];
assign PORT_R_RD_DATA[31:28] = A_read_data[18:15];
end else if (PORT_R_WIDTH == 40) begin
assign PORT_R_RD_DATA[19:0] = B_read_data[19:0];
assign PORT_R_RD_DATA[39:20] = A_read_data[19:0];
end
endgenerate
// port width
wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 :
(PORT_R_WIDTH == 2) ? 3'b001 :
(PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
(PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
(PORT_R_WIDTH == 2) ? 3'b001 :
(PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
(PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 :
(PORT_W_WIDTH == 2) ? 3'b001 :
(PORT_W_WIDTH == 4 || PORT_W_WIDTH == 5) ? 3'b010 :
(PORT_W_WIDTH == 8 || PORT_W_WIDTH == 10) ? 3'b011 :
(PORT_W_WIDTH == 16 || PORT_W_WIDTH == 20) ? 3'b100 : 3'b101;
(PORT_W_WIDTH == 2) ? 3'b001 :
(PORT_W_WIDTH == 4 || PORT_W_WIDTH == 5) ? 3'b010 :
(PORT_W_WIDTH == 8 || PORT_W_WIDTH == 10) ? 3'b011 :
(PORT_W_WIDTH == 16 || PORT_W_WIDTH == 20) ? 3'b100 : 3'b101;
// write modes
wire [1:0] A_write_mode = 2'b00;
wire [1:0] B_write_mode = 2'b00;
RAM1K20 #(
`PARAMS_INIT_LSRAM
`PARAMS_INIT_LSRAM
) _TECHMAP_REPLACE_ (
// port A - read
.A_ADDR(A_address),
.A_BLK_EN(A_BLK_SEL),
.A_CLK(PORT_R_CLK),
.A_DIN(A_write_data),
.A_DOUT(A_read_data),
.A_WEN(A_write_EN),
.A_REN(PORT_R_RD_EN),
.A_WIDTH(A_width),
.A_WMODE(A_write_mode),
.A_BYPASS(1'b1),
.A_DOUT_EN(1'b1),
.A_DOUT_SRST_N(1'b1),
.A_DOUT_ARST_N(1'b1),
// port A - read
.A_ADDR(A_address),
.A_BLK_EN(A_BLK_SEL),
.A_CLK(PORT_R_CLK),
.A_DIN(A_write_data),
.A_DOUT(A_read_data),
.A_WEN(A_write_EN),
.A_REN(PORT_R_RD_EN),
.A_WIDTH(A_width),
.A_WMODE(A_write_mode),
.A_BYPASS(1'b1),
.A_DOUT_EN(1'b1),
.A_DOUT_SRST_N(1'b1),
.A_DOUT_ARST_N(1'b1),
// port B - write
.B_ADDR(B_address),
.B_BLK_EN(B_BLK_SEL),
.B_CLK(PORT_W_CLK),
.B_DIN(B_write_data),
.B_DOUT(B_read_data),
.B_WEN(B_write_EN),
.B_REN(PORT_R_RD_EN),
.B_WIDTH(B_width),
.B_WMODE(B_write_mode),
.B_BYPASS(1'b1),
.B_DOUT_EN(1'b1),
.B_DOUT_SRST_N(1'b1),
.B_DOUT_ARST_N(1'b1),
// Disable ECC for SDP
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
// port B - write
.B_ADDR(B_address),
.B_BLK_EN(B_BLK_SEL),
.B_CLK(PORT_W_CLK),
.B_DIN(B_write_data),
.B_DOUT(B_read_data),
.B_WEN(B_write_EN),
.B_REN(PORT_R_RD_EN),
.B_WIDTH(B_width),
.B_WMODE(B_write_mode),
.B_BYPASS(1'b1),
.B_DOUT_EN(1'b1),
.B_DOUT_SRST_N(1'b1),
.B_DOUT_ARST_N(1'b1),
// Disable ECC for SDP
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
);

62
techlibs/mchp/cells_map.v
View File

@ -18,36 +18,36 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
// DFFs
module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
module \$_DFFE_PN1P_ (input D, C, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
// for sync set/reset registers, we can pass them into ABC9. So we need to follow the simplification idiom
// and map to intermediate cell types
// and map to intermediate cell types
module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
MCHP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
MCHP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
endmodule
module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
MCHP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
MCHP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
endmodule
// LATCHES
module \$_DLATCH_PN0_ (input D, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
endmodule
module \$_DLATCH_PN1_ (input D, R, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
endmodule
module \$_DLATCH_P_ (input D, E, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(1'b1), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(1'b1), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
endmodule
// map intermediate flops to SLE
@ -58,7 +58,7 @@ module MCHP_SYNC_SET_DFF(
input Set,
input En,
output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
endmodule
module MCHP_SYNC_RESET_DFF(
@ -67,7 +67,7 @@ module MCHP_SYNC_RESET_DFF(
input Reset,
input En,
output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Reset), .SD(1'b0), .LAT(1'b0), .Q(Q));
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Reset), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule
`endif
@ -76,29 +76,29 @@ endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
end else
if (WIDTH == 2) begin
CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
end else
if (WIDTH == 3) begin
CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
end else
if (WIDTH == 4) begin
CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
generate
if (WIDTH == 1) begin
CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
end else
if (WIDTH == 2) begin
CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
end else
if (WIDTH == 3) begin
CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
end else
if (WIDTH == 4) begin
CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif

423
techlibs/mchp/cells_sim.v
View File

@ -46,9 +46,9 @@ module CFG1 (
);
parameter [1:0] INIT = 2'h0;
assign Y = INIT >> A;
specify
(A => Y) = 127;
endspecify
specify
(A => Y) = 127;
endspecify
endmodule
(* abc9_lut=2 *)
@ -59,10 +59,10 @@ module CFG2 (
);
parameter [3:0] INIT = 4'h0;
assign Y = INIT >> {B, A};
specify
(A => Y) = 238;
(B => Y) = 127;
endspecify
specify
(A => Y) = 238;
(B => Y) = 127;
endspecify
endmodule
(* abc9_lut=3 *)
@ -74,11 +74,11 @@ module CFG3 (
);
parameter [7:0] INIT = 8'h0;
assign Y = INIT >> {C, B, A};
specify
(A => Y) = 407;
(B => Y) = 238;
(C => Y) = 127;
endspecify
specify
(A => Y) = 407;
(B => Y) = 238;
(C => Y) = 127;
endspecify
endmodule
(* abc9_lut=3 *)
@ -91,12 +91,12 @@ module CFG4 (
);
parameter [15:0] INIT = 16'h0;
assign Y = INIT >> {D, C, B, A};
specify
(A => Y) = 472;
(B => Y) = 407;
(C => Y) = 238;
(D => Y) = 127;
endspecify
specify
(A => Y) = 472;
(B => Y) = 407;
(C => Y) = 238;
(D => Y) = 127;
endspecify
endmodule
module BUFF (
@ -176,12 +176,12 @@ module MCHP_SYNC_SET_DFF(
end
specify
$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
$setup(En, posedge CLK, 109);
$setup(Set, posedge CLK &&& En, 404);
if (En && !Set) (posedge CLK => (Q : 1'b1)) = 303;
if (En && Set) (posedge CLK => (Q : D)) = 303;
endspecify
if (En && Set) (posedge CLK => (Q : D)) = 303;
endspecify
endmodule
(* abc9_flop, lib_whitebox *)
@ -202,12 +202,12 @@ module MCHP_SYNC_RESET_DFF(
end
specify
$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
$setup(En, posedge CLK, 109);
$setup(Reset, posedge CLK &&& En, 404);
if (En && !Reset) (posedge CLK => (Q : 1'b0)) = 303;
if (En && Reset) (posedge CLK => (Q : D)) = 303;
endspecify
if (En && Reset) (posedge CLK => (Q : D)) = 303;
endspecify
endmodule
module SLE (
@ -272,19 +272,19 @@ module ARI1 (
specify
//pin to pin path delay
(A => Y ) = 472;
(B => Y ) = 407;
(C => Y ) = 238;
(D => Y ) = 127;
(A => S ) = 572;
(B => S ) = 507;
(C => S ) = 338;
(D => S ) = 227;
(FCI => S ) = 100;
(A => FCO ) = 522;
(B => FCO ) = 457;
(C => FCO ) = 288;
(D => FCO ) = 177;
(A => Y ) = 472;
(B => Y ) = 407;
(C => Y ) = 238;
(D => Y ) = 127;
(A => S ) = 572;
(B => S ) = 507;
(C => S ) = 338;
(D => S ) = 227;
(FCI => S ) = 100;
(A => FCO ) = 522;
(B => FCO ) = 457;
(C => FCO ) = 288;
(D => FCO ) = 177;
(FCI => FCO ) = 50;
endspecify
endmodule
@ -508,8 +508,8 @@ module CLKBUF (
parameter IOSTD = "";
assign Y = PAD;
specify
(PAD => Y) = 50;
endspecify
(PAD => Y) = 50;
endspecify
endmodule
(* blackbox *)
@ -595,7 +595,7 @@ endmodule
(* blackbox *)
module SYSRESET (
(* iopad_external_pin *)
input DEVRST_N,
input DEVRST_N,
output POWER_ON_RESET_N);
endmodule
@ -603,7 +603,7 @@ endmodule
(* blackbox *)
module XTLOSC (
(* iopad_external_pin *)
input XTL,
input XTL,
output CLKOUT);
parameter [1:0] MODE = 2'h3;
parameter real FREQUENCY = 20.0;
@ -611,191 +611,190 @@ endmodule
(* blackbox *)
module RAM1K18 (
input [13:0] A_ADDR,
input [2:0] A_BLK,
input [13:0] A_ADDR,
input [2:0] A_BLK,
(* clkbuf_sink *)
input A_CLK,
input [17:0] A_DIN,
output [17:0] A_DOUT,
input [1:0] A_WEN,
input [2:0] A_WIDTH,
input A_WMODE,
input A_ARST_N,
input A_DOUT_LAT,
input A_DOUT_ARST_N,
input A_CLK,
input [17:0] A_DIN,
output [17:0] A_DOUT,
input [1:0] A_WEN,
input [2:0] A_WIDTH,
input A_WMODE,
input A_ARST_N,
input A_DOUT_LAT,
input A_DOUT_ARST_N,
(* clkbuf_sink *)
input A_DOUT_CLK,
input A_DOUT_EN,
input A_DOUT_SRST_N,
input A_DOUT_CLK,
input A_DOUT_EN,
input A_DOUT_SRST_N,
input [13:0] B_ADDR,
input [2:0] B_BLK,
input [13:0] B_ADDR,
input [2:0] B_BLK,
(* clkbuf_sink *)
input B_CLK,
input [17:0] B_DIN,
output [17:0] B_DOUT,
input [1:0] B_WEN,
input [2:0] B_WIDTH,
input B_WMODE,
input B_ARST_N,
input B_DOUT_LAT,
input B_DOUT_ARST_N,
input B_CLK,
input [17:0] B_DIN,
output [17:0] B_DOUT,
input [1:0] B_WEN,
input [2:0] B_WIDTH,
input B_WMODE,
input B_ARST_N,
input B_DOUT_LAT,
input B_DOUT_ARST_N,
(* clkbuf_sink *)
input B_DOUT_CLK,
input B_DOUT_EN,
input B_DOUT_SRST_N,
input A_EN,
input B_EN,
input SII_LOCK,
output BUSY);
input B_DOUT_CLK,
input B_DOUT_EN,
input B_DOUT_SRST_N,
input A_EN,
input B_EN,
input SII_LOCK,
output BUSY);
endmodule
(* blackbox *)
module RAM64x18 (
input [9:0] A_ADDR,
input [1:0] A_BLK,
input [2:0] A_WIDTH,
output [17:0] A_DOUT,
input A_DOUT_ARST_N,
input [9:0] A_ADDR,
input [1:0] A_BLK,
input [2:0] A_WIDTH,
output [17:0] A_DOUT,
input A_DOUT_ARST_N,
(* clkbuf_sink *)
input A_DOUT_CLK,
input A_DOUT_EN,
input A_DOUT_LAT,
input A_DOUT_SRST_N,
input A_DOUT_CLK,
input A_DOUT_EN,
input A_DOUT_LAT,
input A_DOUT_SRST_N,
(* clkbuf_sink *)
input A_ADDR_CLK,
input A_ADDR_EN,
input A_ADDR_LAT,
input A_ADDR_SRST_N,
input A_ADDR_ARST_N,
input A_ADDR_CLK,
input A_ADDR_EN,
input A_ADDR_LAT,
input A_ADDR_SRST_N,
input A_ADDR_ARST_N,
input [9:0] B_ADDR,
input [1:0] B_BLK,
input [2:0] B_WIDTH,
output [17:0] B_DOUT,
input B_DOUT_ARST_N,
input [9:0] B_ADDR,
input [1:0] B_BLK,
input [2:0] B_WIDTH,
output [17:0] B_DOUT,
input B_DOUT_ARST_N,
(* clkbuf_sink *)
input B_DOUT_CLK,
input B_DOUT_EN,
input B_DOUT_LAT,
input B_DOUT_SRST_N,
input B_DOUT_CLK,
input B_DOUT_EN,
input B_DOUT_LAT,
input B_DOUT_SRST_N,
(* clkbuf_sink *)
input B_ADDR_CLK,
input B_ADDR_EN,
input B_ADDR_LAT,
input B_ADDR_SRST_N,
input B_ADDR_ARST_N,
input B_ADDR_CLK,
input B_ADDR_EN,
input B_ADDR_LAT,
input B_ADDR_SRST_N,
input B_ADDR_ARST_N,
input [9:0] C_ADDR,
input [9:0] C_ADDR,
(* clkbuf_sink *)
input C_CLK,
input [17:0] C_DIN,
input C_WEN,
input [1:0] C_BLK,
input [2:0] C_WIDTH,
input C_CLK,
input [17:0] C_DIN,
input C_WEN,
input [1:0] C_BLK,
input [2:0] C_WIDTH,
input A_EN,
input B_EN,
input C_EN,
input SII_LOCK,
output BUSY);
input A_EN,
input B_EN,
input C_EN,
input SII_LOCK,
output BUSY);
endmodule
(* blackbox *)
module MACC_PA (
input DOTP,
input SIMD,
input OVFL_CARRYOUT_SEL,
input CLK,
input AL_N,
input [17:0] A,
input A_BYPASS,
input A_SRST_N,
input A_EN,
input [17:0] B,
input B_BYPASS,
input B_SRST_N,
input B_EN,
input [17:0] D,
input D_BYPASS,
input D_ARST_N,
input D_SRST_N,
input D_EN,
input CARRYIN,
input [47:0] C,
input C_BYPASS,
input C_ARST_N,
input C_SRST_N,
input C_EN,
input [47:0] CDIN,
output [47:0] P,
output OVFL_CARRYOUT,
input P_BYPASS,
input P_SRST_N,
input P_EN,
output [47:0] CDOUT,
input PASUB,
input PASUB_BYPASS,
input PASUB_AD_N,
input PASUB_SL_N,
input PASUB_SD_N,
input PASUB_EN,
input [1:0] CDIN_FDBK_SEL,
input CDIN_FDBK_SEL_BYPASS,
input [1:0] CDIN_FDBK_SEL_AD_N,
input CDIN_FDBK_SEL_SL_N,
input [1:0] CDIN_FDBK_SEL_SD_N,
input CDIN_FDBK_SEL_EN,
input ARSHFT17,
input ARSHFT17_BYPASS,
input ARSHFT17_AD_N,
input ARSHFT17_SL_N,
input ARSHFT17_SD_N,
input ARSHFT17_EN,
input SUB,
input SUB_BYPASS,
input SUB_AD_N,
input SUB_SL_N,
input SUB_SD_N,
input SUB_EN
input DOTP,
input SIMD,
input OVFL_CARRYOUT_SEL,
input CLK,
input AL_N,
input [17:0] A,
input A_BYPASS,
input A_SRST_N,
input A_EN,
input [17:0] B,
input B_BYPASS,
input B_SRST_N,
input B_EN,
input [17:0] D,
input D_BYPASS,
input D_ARST_N,
input D_SRST_N,
input D_EN,
input CARRYIN,
input [47:0] C,
input C_BYPASS,
input C_ARST_N,
input C_SRST_N,
input C_EN,
input [47:0] CDIN,
output [47:0] P,
output OVFL_CARRYOUT,
input P_BYPASS,
input P_SRST_N,
input P_EN,
output [47:0] CDOUT,
input PASUB,
input PASUB_BYPASS,
input PASUB_AD_N,
input PASUB_SL_N,
input PASUB_SD_N,
input PASUB_EN,
input [1:0] CDIN_FDBK_SEL,
input CDIN_FDBK_SEL_BYPASS,
input [1:0] CDIN_FDBK_SEL_AD_N,
input CDIN_FDBK_SEL_SL_N,
input [1:0] CDIN_FDBK_SEL_SD_N,
input CDIN_FDBK_SEL_EN,
input ARSHFT17,
input ARSHFT17_BYPASS,
input ARSHFT17_AD_N,
input ARSHFT17_SL_N,
input ARSHFT17_SD_N,
input ARSHFT17_EN,
input SUB,
input SUB_BYPASS,
input SUB_AD_N,
input SUB_SL_N,
input SUB_SD_N,
input SUB_EN
);
endmodule
(* blackbox *)
module RAM1K20 (
input [13:0] A_ADDR,
input [2:0] A_BLK_EN,
input A_CLK,
input [19:0] A_DIN,
output [19:0] A_DOUT,
input [1:0] A_WEN,
input A_REN,
input [2:0] A_WIDTH,
input [1:0] A_WMODE,
input A_BYPASS,
input A_DOUT_EN,
input A_DOUT_SRST_N,
input A_DOUT_ARST_N,
input [13:0] B_ADDR,
input [2:0] B_BLK_EN,
input B_CLK,
input [19:0] B_DIN,
output [19:0] B_DOUT,
input [1:0] B_WEN,
input B_REN,
input [2:0] B_WIDTH,
input [1:0] B_WMODE,
input B_BYPASS,
input B_DOUT_EN,
input B_DOUT_SRST_N,
input B_DOUT_ARST_N,
input ECC_EN,
input ECC_BYPASS,
output SB_CORRECT,
output DB_DETECT,
input BUSY_FB,
output ACCESS_BUSY
input [13:0] A_ADDR,
input [2:0] A_BLK_EN,
input A_CLK,
input [19:0] A_DIN,
output [19:0] A_DOUT,
input [1:0] A_WEN,
input A_REN,
input [2:0] A_WIDTH,
input [1:0] A_WMODE,
input A_BYPASS,
input A_DOUT_EN,
input A_DOUT_SRST_N,
input A_DOUT_ARST_N,
input [13:0] B_ADDR,
input [2:0] B_BLK_EN,
input B_CLK,
input [19:0] B_DIN,
output [19:0] B_DOUT,
input [1:0] B_WEN,
input B_REN,
input [2:0] B_WIDTH,
input [1:0] B_WMODE,
input B_BYPASS,
input B_DOUT_EN,
input B_DOUT_SRST_N,
input B_DOUT_ARST_N,
input ECC_EN,
input ECC_BYPASS,
output SB_CORRECT,
output DB_DETECT,
input BUSY_FB,
output ACCESS_BUSY
);
parameter INIT0 = 1024'h0;
parameter INIT1 = 1024'h0;
@ -821,29 +820,29 @@ endmodule
(* blackbox *)
module RAM64x12 (
input R_CLK,
input [5:0] R_ADDR,
input R_ADDR_BYPASS,
input R_CLK,
input [5:0] R_ADDR,
input R_ADDR_BYPASS,
input R_ADDR_EN,
input R_ADDR_SL_N,
input R_ADDR_SD,
input R_ADDR_AL_N,
input R_ADDR_AD_N,
input BLK_EN,
output [11:0] R_DATA,
input R_DATA_BYPASS,
input BLK_EN,
output [11:0] R_DATA,
input R_DATA_BYPASS,
input R_DATA_EN,
input R_DATA_SL_N,
input R_DATA_SD,
input R_DATA_AL_N,
input R_DATA_AD_N,
input W_CLK,
input [5:0] W_ADDR,
input [11:0] W_DATA,
input W_EN,
input W_CLK,
input [5:0] W_ADDR,
input [11:0]W_DATA,
input W_EN,
input BUSY_FB,
output ACCESS_BUSY
input BUSY_FB,
output ACCESS_BUSY
);
endmodule

6
techlibs/mchp/mchp_dffopt.cc
View File

@ -166,11 +166,11 @@ lut_sigin_done:
// Iterate through FFs.
for (auto cell : module->selected_cells())
{
if (!cell->type.in(ID(SLE))) // not a SLE
if (!cell->type.in(ID(SLE))) // not a SLE
continue;
if (cell->getPort(ID(LAT)).is_fully_ones()) // skip latch
continue;
continue;
if (cell->get_bool_attribute(ID::keep)) // keep attribute
continue;
if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF

108
techlibs/mchp/pf_dsp_map.v
View File

@ -24,71 +24,71 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
parameter Y_WIDTH = 0;
wire [47:0] P_48;
// For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
// https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
// For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
// https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
MACC_PA _TECHMAP_REPLACE_ (
.DOTP(1'b0),
.SIMD(1'b0),
.OVFL_CARRYOUT_SEL(1'b0),
.SIMD(1'b0),
.OVFL_CARRYOUT_SEL(1'b0),
.AL_N(1'b1),
.A(A),
.A_BYPASS(1'b1),
.A_SRST_N(1'b1),
.A_EN(1'b1),
.AL_N(1'b1),
.A(A),
.A_BYPASS(1'b1),
.A_SRST_N(1'b1),
.A_EN(1'b1),
.B(B),
.B_BYPASS(1'b1),
.B_SRST_N(1'b1),
.B_EN(1'b1),
.B(B),
.B_BYPASS(1'b1),
.B_SRST_N(1'b1),
.B_EN(1'b1),
.D(18'b0),
.D_BYPASS(1'b1),
.D_ARST_N(1'b1),
.D_SRST_N(1'b1),
.D_EN(1'b1),
.CARRYIN(1'b0),
.C(48'b0),
.C_BYPASS(1'b1),
.C_ARST_N(1'b1),
.C_SRST_N(1'b1),
.C_EN(1'b1),
.D(18'b0),
.D_BYPASS(1'b1),
.D_ARST_N(1'b1),
.D_SRST_N(1'b1),
.D_EN(1'b1),
.CARRYIN(1'b0),
.C(48'b0),
.C_BYPASS(1'b1),
.C_ARST_N(1'b1),
.C_SRST_N(1'b1),
.C_EN(1'b1),
.P(P_48),
.P(P_48),
.P_BYPASS(1'b1),
.P_SRST_N(1'b1),
.P_EN(1'b1),
.P_BYPASS(1'b1),
.P_SRST_N(1'b1),
.P_EN(1'b1),
.PASUB(1'b0),
.PASUB_BYPASS(1'b1),
.PASUB_AD_N(1'b0),
.PASUB_SL_N(1'b1),
.PASUB_SD_N(1'b0),
.PASUB_EN(1'b1),
.PASUB(1'b0),
.PASUB_BYPASS(1'b1),
.PASUB_AD_N(1'b0),
.PASUB_SL_N(1'b1),
.PASUB_SD_N(1'b0),
.PASUB_EN(1'b1),
.CDIN_FDBK_SEL(2'b00),
.CDIN_FDBK_SEL_BYPASS(1'b1),
.CDIN_FDBK_SEL_AD_N(2'b00),
.CDIN_FDBK_SEL_SL_N(1'b1),
.CDIN_FDBK_SEL_SD_N(2'b00),
.CDIN_FDBK_SEL_EN(1'b1),
.CDIN_FDBK_SEL(2'b00),
.CDIN_FDBK_SEL_BYPASS(1'b1),
.CDIN_FDBK_SEL_AD_N(2'b00),
.CDIN_FDBK_SEL_SL_N(1'b1),
.CDIN_FDBK_SEL_SD_N(2'b00),
.CDIN_FDBK_SEL_EN(1'b1),
.ARSHFT17(1'b0),
.ARSHFT17_BYPASS(1'b1),
.ARSHFT17_AD_N(1'b0),
.ARSHFT17_SL_N(1'b1),
.ARSHFT17_SD_N(1'b0),
.ARSHFT17_EN(1'b1),
.ARSHFT17(1'b0),
.ARSHFT17_BYPASS(1'b1),
.ARSHFT17_AD_N(1'b0),
.ARSHFT17_SL_N(1'b1),
.ARSHFT17_SD_N(1'b0),
.ARSHFT17_EN(1'b1),
.SUB(1'b0),
.SUB_BYPASS(1'b1),
.SUB_AD_N(1'b0),
.SUB_SL_N(1'b1),
.SUB_SD_N(1'b0),
.SUB_EN(1'b1)
.SUB(1'b0),
.SUB_BYPASS(1'b1),
.SUB_AD_N(1'b0),
.SUB_SL_N(1'b1),
.SUB_SD_N(1'b0),
.SUB_EN(1'b1)
);
assign Y = P_48;

20
techlibs/mchp/tests/Registers/Registers.v
View File

@ -17,21 +17,21 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module Registers(
input clk,
input en,
input rst,
input D,
output Q
input clk,
input en,
input rst,
input D,
output Q
);
parameter LOAD_DATA = 1;
// active low async reset
always @(posedge clk, negedge rst) begin
if (rst == 0) begin
Q <= LOAD_DATA;
end else if(en) begin
Q <= D;
end
if (rst == 0) begin
Q <= LOAD_DATA;
end else if(en) begin
Q <= D;
end
end

10
techlibs/mchp/tests/carryout/carryout.v
View File

@ -25,10 +25,10 @@ input [n:0] a;
input [n:0] b;
input [n-1:0] c;
always @(a,b,c)
begin
{cout,out} = a * b + c;
end
always @(a,b,c)
begin
{cout,out} = a * b + c;
end
endmodule

12
techlibs/mchp/tests/cascade/cascade.v
View File

@ -17,13 +17,13 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module cascade(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output signed [11:0] out_P,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output signed [11:0] out_P,
input signed [4:0] casA,
input signed [4:0] casB
input signed [4:0] casA,
input signed [4:0] casB
);

20
techlibs/mchp/tests/dff_opt/dff_opt.v
View File

@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module dff_opt(
input clk,
input [1:0] D_comb,
input [1:0] EN_comb,
input [1:0] RST_comb,
output bar
input clk,
input [1:0] D_comb,
input [1:0] EN_comb,
input [1:0] RST_comb,
output bar
);
// DFF with enable that can be merged into D
@ -32,11 +32,11 @@ assign bar = foo;
// sync reset
always@(posedge clk) begin
if (&RST_comb) begin
foo <= 0;
end else begin
foo <= &D_comb;
end
if (&RST_comb) begin
foo <= 0;
end else begin
foo <= &D_comb;
end
end
endmodule

10
techlibs/mchp/tests/full_dsp/full_dsp.v
View File

@ -16,12 +16,12 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module full_dsp(
input signed[5:0] in_A,
input signed [4:0] in_B,
input signed [11:0] in_C,
input signed [4:0] in_D,
input signed[5:0] in_A,
input signed [4:0] in_B,
input signed [11:0] in_C,
input signed [4:0] in_D,
output signed [12:0] out_Y
output signed [12:0] out_Y
);
assign out_Y = ((in_D + in_B)*in_A)+in_C;

6
techlibs/mchp/tests/large_mult/large_mult.v
View File

@ -17,9 +17,9 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module large_mult(
input signed [20:0] in1,
input signed [17:0] in2,
output signed [38:0] out1
input signed [20:0] in1,
input signed [17:0] in2,
output signed [38:0] out1
);
assign out1 = in1 * in2;
endmodule

26
techlibs/mchp/tests/mac/mac.v
View File

@ -17,27 +17,27 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module mac(
input clk,
input signed [4:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg signed [11:0] out_P,
input clk,
input signed [4:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg signed [11:0] out_P,
input srst_P,
input srst_P,
input signed [4:0] casA,
input signed [4:0] casB
input signed [4:0] casA,
input signed [4:0] casB
);
// sync reset P
always@(posedge clk) begin
if (~srst_P) begin
out_P <= 12'h000;
end else begin
out_P <= in_A * (in_B + in_D) + out_P;
end
if (~srst_P) begin
out_P <= 12'h000;
end else begin
out_P <= in_A * (in_B + in_D) + out_P;
end
end
endmodule

8
techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
View File

@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module postAdd_mult(
input signed[17:0] in_A,
input signed [17:0] in_B,
input signed [17:0] in_C,
input signed[17:0] in_A,
input signed [17:0] in_B,
input signed [17:0] in_C,
output signed [35:0] out_Y
output signed [35:0] out_Y
);
assign out_Y = (in_B*in_A)+in_C;

12
techlibs/mchp/tests/post_adder/post_adder.v
View File

@ -17,12 +17,12 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module post_adder(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input signed [11:0] in_C,
output [12:0] out_Y
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input signed [11:0] in_C,
output [12:0] out_Y
);
assign out_Y = (in_D + in_B) * in_A + in_C;

10
techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
View File

@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module pre_adder_dsp(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output [11:0] out_Y
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output [11:0] out_Y
);
assign out_Y = in_A * (in_B + in_D);

10
techlibs/mchp/tests/ram_SDP/ram_SDP.v
View File

@ -28,11 +28,11 @@ output reg [d_width-1:0] q;
reg [d_width-1:0] mem [mem_depth-1:0];
always @(posedge clk) begin
if (we) begin
mem[waddr] <= data;
end else begin
q <= mem[waddr];
end
if (we) begin
mem[waddr] <= data;
end else begin
q <= mem[waddr];
end
end
endmodule

10
techlibs/mchp/tests/ram_TDP/ram_TDP.v
View File

@ -27,11 +27,11 @@ reg [addr_width - 1 : 0] addra_reg, addrb_reg;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
always @ (posedge clka)
begin
addra_reg <= addra;
if(wea)
mem[addra] <= dataina;
end
begin
addra_reg <= addra;
if(wea)
mem[addra] <= dataina;
end
always @ (posedge clkb)
begin

6
techlibs/mchp/tests/reduce/reduce.v
View File

@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module reduce(
input [7:0] data,
output Y
input [7:0] data,
output Y
);
);
assign Y = ^data;

96
techlibs/mchp/tests/reg_c/reg_c.v
View File

@ -17,34 +17,34 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module reg_c(
input clk,
input clk,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input arst_D,
// active low
input arst_D,
input srst_C,
input arst_C,
input srst_C,
input arst_C,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_C,
input signed [4:0] in_D,
output reg [11:0] out_P
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_C,
input signed [4:0] in_D,
output reg [11:0] out_P
);
@ -69,54 +69,54 @@ reg signed [4:0] reg_D;
// sync reset A
always@(posedge clk) begin
// if (~srst_A_N) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
// if (~srst_A_N) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
end
// sync reset B
always@(posedge clk) begin
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
end
// async reset D
always@(posedge clk, negedge arst_D) begin
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
end
// sync reset C
always@(posedge clk) begin
if (srst_C_N) begin
reg_C = 5'b00000;
end else begin
reg_C = in_C;
end
if (srst_C_N) begin
reg_C = 5'b00000;
end else begin
reg_C = in_C;
end
end
// sync reset P
always@(posedge clk) begin
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D) + reg_C;
end
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D) + reg_C;
end
end
endmodule

76
techlibs/mchp/tests/reg_test/reg_test.v
View File

@ -17,28 +17,28 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module reg_test(
input clk,
input clk,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input arst_D,
// active low
input arst_D,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg [11:0] out_P
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg [11:0] out_P
);
@ -60,38 +60,38 @@ reg signed [4:0] reg_D;
// sync reset A
always@(posedge clk) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
end
// sync reset B
always@(posedge clk) begin
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
end
// async reset D
always@(posedge clk, negedge arst_D) begin
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
end
// sync reset P
always@(posedge clk) begin
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D);
end
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D);
end
end
endmodule

8
techlibs/mchp/tests/signed_mult/signed_mult.v
View File

@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module signed_mult(
input signed [17:0] in_A,
input signed [17:0] in_B,
output signed [35:0] out_Y
input signed [17:0] in_A,
input signed [17:0] in_B,
output signed [35:0] out_Y
);
assign out_Y = in_A * in_B;

6
techlibs/mchp/tests/simple_ram/simple_ram.v
View File

@ -29,9 +29,9 @@ reg [19:0] mem [0:1023] ;
assign dout = mem[addr_reg];
always@(posedge clk) begin
addr_reg <= addr;
if(wr)
mem[addr]<= din;
addr_reg <= addr;
if(wr)
mem[addr]<= din;
end
endmodule

8
techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
View File

@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module unsigned_mult(
input [10:0] in_A,
input signed [10:0] in_B,
output [21:0] out_Y
input [10:0] in_A,
input signed [10:0] in_B,
output [21:0] out_Y
);
assign out_Y = in_A * in_B;

4
techlibs/mchp/tests/uram_ar/uram_ar.v
View File

@ -30,8 +30,8 @@ reg [d_width-1:0] mem [mem_depth-1:0];
assign q = mem[waddr];
always @(posedge clk) begin
if (we)
mem[waddr] <= data;
if (we)
mem[waddr] <= data;
end

4
techlibs/mchp/tests/uram_sr/uram_sr.v
View File

@ -26,7 +26,7 @@ reg [5:0] raddr_reg;
reg [11:0] mem [0:63];
assign dout = mem[raddr_reg];
always@(posedge clk) begin
raddr_reg <= raddr; if(wr)
mem[waddr]<= din;
raddr_reg <= raddr; if(wr)
mem[waddr]<= din;
end
endmodule

40
techlibs/mchp/tests/widemux/widemux.v
View File

@ -17,31 +17,31 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module widemux(
input [3:0] data,
input S0,
input S1,
output Y
input [3:0] data,
input S0,
input S1,
output Y
);
);
wire A, B;
wire A, B;
always @ (*) begin
if (S0)begin
A = data[1];
B = data[3];
end else begin
A = data[0];
B = data[2];
end
always @ (*) begin
if (S0)begin
A = data[1];
B = data[3];
end else begin
A = data[0];
B = data[2];
end
if (S1)begin
Y = A;
end else begin
Y = B;
end
if (S1)begin
Y = A;
end else begin
Y = B;
end
end
end
endmodule

20
techlibs/mchp/uSRAM.txt
View File

@ -23,21 +23,21 @@ ram block $__uSRAM_AR_ {
# INIT supported
init any;
abits 6;
widths 12 per_port;
abits 6;
widths 12 per_port;
# single write enable wire
# single write enable wire
port sw "W" {
clock posedge;
# collision not supported, but write takes precedence and read data is invalid while writing to
# the same address
# collision not supported, but write takes precedence and read data is invalid while writing to
# the same address
wrtrans all new;
optional;
}
port ar "R" {
optional;
optional;
}
}
@ -48,14 +48,14 @@ ram block $__uSRAM_SR_ {
cost 42;
init any;
abits 6;
widths 12 per_port;
init any;
abits 6;
widths 12 per_port;
port sw "W" {
clock posedge;
# collision not supported
# collision not supported
wrtrans all new;
optional;

46
techlibs/mchp/uSRAM_map.v
View File

@ -17,7 +17,7 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
// See document PolarFire Family Fabric User Guide
// section 4.2 for port list.
// section 4.2 for port list.
// Asynchronous read
module $__uSRAM_AR_ (...);
@ -82,36 +82,36 @@ input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
input PORT_W_WR_EN;
// Read port clock and enable signal
// that async read uSRAM doesn't have
// that async read uSRAM doesn't have
input PORT_R_CLK;
input PORT_R_RD_EN;
input [ADDR_BITS-1:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
RAM64x12 _TECHMAP_REPLACE_ (
.R_CLK(PORT_R_CLK),
.R_ADDR(PORT_R_ADDR),
.R_ADDR_BYPASS(1'b0),
.R_ADDR_EN(PORT_R_RD_EN),
.R_ADDR_SL_N(1'b1),
.R_ADDR_SD(1'b0),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AD_N(1'b0),
.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
.R_DATA(PORT_R_RD_DATA),
.R_DATA_BYPASS(1'b1),
.R_DATA_EN(1'b0),
.R_DATA_SL_N(1'b1),
.R_DATA_SD(1'b0),
.R_DATA_AL_N(1'b1),
.R_DATA_AD_N(1'b0),
.R_CLK(PORT_R_CLK),
.R_ADDR(PORT_R_ADDR),
.R_ADDR_BYPASS(1'b0),
.R_ADDR_EN(PORT_R_RD_EN),
.R_ADDR_SL_N(1'b1),
.R_ADDR_SD(1'b0),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AD_N(1'b0),
.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
.R_DATA(PORT_R_RD_DATA),
.R_DATA_BYPASS(1'b1),
.R_DATA_EN(1'b0),
.R_DATA_SL_N(1'b1),
.R_DATA_SD(1'b0),
.R_DATA_AL_N(1'b1),
.R_DATA_AD_N(1'b0),
.W_CLK(PORT_W_CLK),
.W_ADDR(PORT_W_ADDR),
.W_DATA(PORT_W_WR_DATA),
.W_EN(PORT_W_WR_EN),
.W_CLK(PORT_W_CLK),
.W_ADDR(PORT_W_ADDR),
.W_DATA(PORT_W_WR_DATA),
.W_EN(PORT_W_WR_EN),
.BUSY_FB(1'b0)
.BUSY_FB(1'b0)
);
endmodule