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opt_expr: change info message
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@ -515,7 +515,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (!cells.sort()) {
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// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
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// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
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log("Couldn't topologically sort cells, Yosys performance may be degraded.\nRunning 'check' is recommended.\n");
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log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module));
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}
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for (auto cell : cells.sorted)
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