mirror of https://github.com/YosysHQ/yosys.git
check: Use cell edges data in detecting combinational loops
This commit is contained in:
Martin Povišer
parent
c5ae74af34
commit
fa74d0bd1a
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@ -19,6 +19,7 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celledges.h"
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#include "kernel/celltypes.h"
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#include "kernel/utils.h"
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@ -102,6 +103,7 @@ struct CheckPass : public Pass {
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SigMap sigmap(module);
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dict<SigBit, vector<string>> wire_drivers;
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dict<SigBit, Cell *> driver_cells;
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dict<SigBit, int> wire_drivers_count;
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pool<SigBit> used_wires;
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TopoSort<std::pair<RTLIL::IdString, int>> topo;
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@ -149,6 +151,46 @@ struct CheckPass : public Pass {
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}
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}
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struct CircuitEdgesDatabase : AbstractCellEdgesDatabase {
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TopoSort<std::pair<RTLIL::IdString, int>> &topo;
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SigMap sigmap;
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CircuitEdgesDatabase(TopoSort<std::pair<RTLIL::IdString, int>> &topo, SigMap &sigmap)
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: topo(topo), sigmap(sigmap) {}
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit,
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RTLIL::IdString to_port, int to_bit, int) override {
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SigBit from = sigmap(cell->getPort(from_port))[from_bit];
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SigBit to = sigmap(cell->getPort(to_port))[to_bit];
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if (from.wire && to.wire)
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topo.edge(std::make_pair(from.wire->name, from.offset), std::make_pair(to.wire->name, to.offset));
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}
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bool add_edges_from_cell(Cell *cell) {
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if (AbstractCellEdgesDatabase::add_edges_from_cell(cell))
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return true;
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// We don't have accurate cell edges, do the fallback of all input-output pairs
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for (auto &conn : cell->connections()) {
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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topo.edge(std::make_pair(bit.wire->name, bit.offset),
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std::make_pair(cell->name, -1));
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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topo.edge(std::make_pair(cell->name, -1),
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std::make_pair(bit.wire->name, bit.offset));
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}
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return true;
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}
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};
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CircuitEdgesDatabase edges_db(topo, sigmap);
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for (auto cell : module->cells())
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{
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if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
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@ -157,31 +199,29 @@ struct CheckPass : public Pass {
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counter++;
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cell_allowed:;
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}
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for (auto &conn : cell->connections()) {
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SigSpec sig = sigmap(conn.second);
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bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
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if (cell->input(conn.first))
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for (auto bit : sig)
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if (bit.wire) {
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if (logic_cell && bit.wire)
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topo.edge(std::make_pair(bit.wire->name, bit.offset),
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std::make_pair(cell->name, -1));
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used_wires.insert(bit);
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}
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if (cell->output(conn.first))
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for (int i = 0; i < GetSize(sig); i++) {
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if (logic_cell && sig[i].wire)
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topo.edge(std::make_pair(cell->name, -1),
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std::make_pair(sig[i].wire->name, sig[i].offset));
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if (sig[i].wire || !cell->input(conn.first))
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wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
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log_id(conn.first), i, log_id(cell), log_id(cell->type)));
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}
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if (!cell->input(conn.first) && cell->output(conn.first))
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for (auto bit : sig)
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if (bit.wire) wire_drivers_count[bit]++;
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for (auto &conn : cell->connections()) {
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bool input = cell->input(conn.first);
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bool output = cell->output(conn.first);
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SigSpec sig = sigmap(conn.second);
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for (int i = 0; i < sig.size(); i++) {
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SigBit bit = sig[i];
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if (input && bit.wire)
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used_wires.insert(bit);
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if (output && !input && bit.wire)
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wire_drivers_count[bit]++;
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if (output && (bit.wire || !input))
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wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", log_id(conn.first), i,
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log_id(cell), log_id(cell->type)));
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if (output)
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driver_cells[bit] = cell;
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}
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}
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if (yosys_celltypes.cell_evaluable(cell->type))
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edges_db.add_edges_from_cell(cell);
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}
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pool<SigBit> init_bits;
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@ -238,27 +278,68 @@ struct CheckPass : public Pass {
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topo.sort();
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for (auto &loop : topo.loops) {
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string message = stringf("found logic loop in module %s:\n", log_id(module));
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// `loop` only contains wire bits, or an occassional special helper node for cells for
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// which we have done the edges fallback. The cell and its ports that led to an edge is
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// an information we need to recover now. For that we need to have the previous wire bit
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// of the loop at hand.
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SigBit prev;
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for (auto it = loop.rbegin(); it != loop.rend(); it++)
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if (it->second != -1) { // skip the fallback helper nodes
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prev = SigBit(module->wire(it->first), it->second);
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break;
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}
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log_assert(prev != SigBit());
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for (auto &pair : loop) {
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RTLIL::AttrObject *obj;
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if (pair.second == -1)
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obj = module->cell(pair.first);
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else
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obj = module->wire(pair.first);
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log_assert(obj);
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std::string src;
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if (obj->has_attribute(ID::src)) {
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std::string src_attr = obj->get_src_attribute();
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src = stringf(" source: %s", src_attr.c_str());
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continue; // helper node for edges fallback, we can ignore it
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struct MatchingEdgePrinter : AbstractCellEdgesDatabase {
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std::string &message;
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SigMap &sigmap;
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SigBit from, to;
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int nhits;
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const int HITS_LIMIT = 3;
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MatchingEdgePrinter(std::string &message, SigMap &sigmap, SigBit from, SigBit to)
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: message(message), sigmap(sigmap), from(from), to(to), nhits(0) {}
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit,
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RTLIL::IdString to_port, int to_bit, int) override {
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SigBit edge_from = sigmap(cell->getPort(from_port))[from_bit];
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SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit];
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if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT)
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message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit,
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log_id(to_port), to_bit);
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if (nhits == HITS_LIMIT)
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message += " ...\n";
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}
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};
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Wire *wire = module->wire(pair.first);
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log_assert(wire);
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SigBit bit(module->wire(pair.first), pair.second);
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log_assert(driver_cells.count(bit));
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Cell *driver = driver_cells.at(bit);
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std::string driver_src;
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if (driver->has_attribute(ID::src)) {
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std::string src_attr = driver->get_src_attribute();
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driver_src = stringf(" source: %s", src_attr.c_str());
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}
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if (pair.second == -1) {
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Cell *cell = module->cell(pair.first);
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log_assert(cell);
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message += stringf(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), src.c_str());
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} else {
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Wire *wire = module->wire(pair.first);
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log_assert(wire);
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message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), src.c_str());
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message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str());
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MatchingEdgePrinter printer(message, sigmap, prev, bit);
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printer.add_edges_from_cell(driver);
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std::string wire_src;
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if (wire->has_attribute(ID::src)) {
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std::string src_attr = wire->get_src_attribute();
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wire_src = stringf(" source: %s", src_attr.c_str());
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}
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message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src.c_str());
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prev = bit;
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}
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log_warning("%s", message.c_str());
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counter++;
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