mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4188 from povik/dlatch-bwmux
proc_dlatch: Include `$bwmux` among considered mux cells
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commit
aebb7a0c4d
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@ -46,7 +46,7 @@ struct proc_dlatch_db_t
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($mux), ID($pmux)))
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if (cell->type.in(ID($mux), ID($pmux), ID($bwmux)))
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{
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auto sig_y = sigmap(cell->getPort(ID::Y));
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for (int i = 0; i < GetSize(sig_y); i++)
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@ -186,6 +186,8 @@ struct proc_dlatch_db_t
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Cell *cell = it->second.first;
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int index = it->second.second;
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log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux)));
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bool is_bwmux = (cell->type == ID($bwmux));
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SigSpec sig_a = sigmap(cell->getPort(ID::A));
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SigSpec sig_b = sigmap(cell->getPort(ID::B));
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SigSpec sig_s = sigmap(cell->getPort(ID::S));
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@ -200,12 +202,16 @@ struct proc_dlatch_db_t
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sig[index] = State::Sx;
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cell->setPort(ID::A, sig);
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}
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for (int i = 0; i < GetSize(sig_s); i++)
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n = make_inner(sig_s[i], State::S0, n);
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if (!is_bwmux) {
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for (int i = 0; i < GetSize(sig_s); i++)
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n = make_inner(sig_s[i], State::S0, n);
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} else {
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n = make_inner(sig_s[index], State::S0, n);
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}
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children.insert(n);
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}
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for (int i = 0; i < GetSize(sig_s); i++) {
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for (int i = 0; i < (is_bwmux ? 1 : GetSize(sig_s)); i++) {
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n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
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if (n != false_node) {
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if (set_undef && sig_b[i*width + index] == needle) {
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@ -213,7 +219,7 @@ struct proc_dlatch_db_t
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sig[i*width + index] = State::Sx;
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cell->setPort(ID::B, sig);
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}
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children.insert(make_inner(sig_s[i], State::S1, n));
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children.insert(make_inner(sig_s[is_bwmux ? index : i], State::S1, n));
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}
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}
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