mirror of https://github.com/YosysHQ/yosys.git
cellmatch: New pass
This commit is contained in:
Martin Povišer
Emil J. Tywoniak
parent
2631c7e918
commit
86e1080f05
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@ -48,6 +48,7 @@ OBJS += passes/techmap/dfflegalize.o
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OBJS += passes/techmap/dffunmap.o
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OBJS += passes/techmap/flowmap.o
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OBJS += passes/techmap/extractinv.o
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OBJS += passes/techmap/cellmatch.o
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endif
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ifeq ($(DISABLE_SPAWN),0)
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@ -0,0 +1,340 @@
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#include "kernel/celltypes.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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#include <algorithm>
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USING_YOSYS_NAMESPACE
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YOSYS_NAMESPACE_BEGIN
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// return module's inputs in canonical order
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SigSpec module_inputs(Module *m)
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{
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SigSpec ret;
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for (auto port : m->ports) {
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Wire *w = m->wire(port);
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if (!w->port_input)
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continue;
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if (w->width != 1)
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log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n",
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log_id(w), log_id(m));
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ret.append(w);
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}
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return ret;
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}
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// return module's outputs in canonical order
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SigSpec module_outputs(Module *m)
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{
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SigSpec ret;
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for (auto port : m->ports) {
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Wire *w = m->wire(port);
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if (!w->port_output)
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continue;
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if (w->width != 1)
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log_error("Unsupported wide port (%s) of non-unit width found in module %s.\n",
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log_id(w), log_id(m));
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ret.append(w);
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}
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return ret;
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}
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uint64_t permute_lut(uint64_t lut, const std::vector<int> &varmap)
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{
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int k = varmap.size();
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uint64_t ret = 0;
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for (int j = 0; j < 1 << k; j++) {
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int m = 0;
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for (int l = 0; l < k; l++)
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if (j & 1 << l)
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m |= 1 << varmap[l];
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if (lut & 1 << m)
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ret |= 1 << j;
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}
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return ret;
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}
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uint64_t p_class(int k, uint64_t lut)
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{
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std::vector<int> map;
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for (int j = 0; j < k; j++)
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map.push_back(j);
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uint64_t repr = ~(uint64_t) 0;
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std::vector<int> repr_vars;
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while (true) {
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uint64_t perm = permute_lut(lut, map);
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if (perm <= repr) {
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repr = perm;
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repr_vars = map;
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}
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if (!std::next_permutation(map.begin(), map.end()))
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break;
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}
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return repr;
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}
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bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
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{
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SigMap sigmap(m);
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CellTypes ff_types;
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ff_types.setup_stdcells_mem();
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dict<SigBit, Cell*> driver;
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for (auto cell : m->selected_cells()) {
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if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
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continue;
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if (ff_types.cell_known(cell->type)) {
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log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m));
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return false;
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}
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if (!cell->type.in(ID($_NOT_), ID($_AND_)))
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log_error("Unsupported cell in module '%s': %s of type %s\n",
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log_id(m), log_id(cell), log_id(cell->type));
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driver[sigmap(cell->getPort(ID::Y))] = cell;
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}
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TopoSort<Cell*> sort;
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for (auto cell : m->cells())
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if (cell->type.in(ID($_NOT_), ID($_AND_))) {
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sort.node(cell);
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SigSpec inputs = cell->type == ID($_AND_)
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? SigSpec({cell->getPort(ID::B), cell->getPort(ID::A)})
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: cell->getPort(ID::A);
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for (auto bit : sigmap(inputs))
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if (driver.count(bit))
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sort.edge(driver.at(bit), cell);
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}
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if (!sort.sort())
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log_error("Module %s contains combinational loops.\n", log_id(m));
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dict<SigBit, uint64_t> states;
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states[State::S0] = 0;
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states[State::S1] = ~(uint64_t) 1;
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{
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uint64_t sieves[6] = {
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0xaaaaaaaaaaaaaaaa,
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0xcccccccccccccccc,
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0xf0f0f0f0f0f0f0f0,
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0xff00ff00ff00ff00,
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0xffff0000ffff0000,
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0xffffffff00000000,
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};
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SigSpec inputs = sigmap(module_inputs(m));
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if (inputs.size() > 6) {
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log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
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return false;
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}
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for (int i = 0; i < inputs.size(); i++)
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states[inputs[i]] = sieves[i] & ((((uint64_t) 1) << (1 << inputs.size())) - 1);
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}
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for (auto cell : sort.sorted) {
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if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
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continue;
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if (cell->type == ID($_AND_)) {
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SigSpec a = sigmap(cell->getPort(ID::A));
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SigSpec b = sigmap(cell->getPort(ID::B));
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if (!states.count(a) || !states.count(b))
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log_error("Cell %s in module %s sources an undriven wire!",
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log_id(cell), log_id(m));
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states[sigmap(cell->getPort(ID::Y))] = \
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states.at(a) & states.at(b);
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} else if (cell->type == ID($_NOT_)) {
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SigSpec a = sigmap(cell->getPort(ID::A));
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if (!states.count(a))
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log_error("Cell %s in module %s sources an undriven wire!",
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log_id(cell), log_id(m));
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states[sigmap(cell->getPort(ID::Y))] = ~states.at(a);
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} else {
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log_abort();
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}
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}
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for (auto bit : module_outputs(m)) {
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if (!states.count(sigmap(bit)))
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log_error("Output port %s in module %s is undriven!",
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log_signal(bit), log_id(m));
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luts.push_back(states.at(sigmap(bit)));
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}
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return true;
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}
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struct CellmatchPass : Pass {
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CellmatchPass() : Pass("cellmatch", "match cells to their targets in cell library") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" cellmatch -lib <design> [module selection]\n");
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log("\n");
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log("This pass identifies functionally equivalent counterparts between each of the\n");
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log("selected modules and a module from the secondary design <design>. For every such\n");
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log("correspondence found, a techmap rule is generated for mapping instances of the\n");
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log("former to instances of the latter. This techmap rule is saved in yet another\n");
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log("design called '$cellmatch_map', which is created if non-existent.\n");
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log("\n");
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log("This pass restricts itself to combinational modules which must be modeled with an\n");
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log("and-inverter graph. Run 'aigmap' first if necessary. Modules are functionally\n");
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log("equivalent as long as their truth tables are identical upto a permutation of\n");
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log("inputs and outputs. The number of inputs is limited to 6.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *d) override
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{
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log_header(d, "Executing CELLMATCH pass. (match cells)\n");
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size_t argidx;
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bool lut_attrs = false;
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Design *lib = NULL;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-lut_attrs") {
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// an undocumented debugging option
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lut_attrs = true;
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} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
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if (!saved_designs.count(args[++argidx]))
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log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
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lib = saved_designs.at(args[argidx]);
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} else {
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break;
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}
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}
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extra_args(args, argidx, d);
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if (!lib && !lut_attrs)
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log_cmd_error("Missing required -lib option.\n");
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struct Target {
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Module *module;
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std::vector<uint64_t> luts;
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};
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dict<pool<uint64_t>, std::vector<Target>> targets;
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if (lib)
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for (auto m : lib->modules()) {
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pool<uint64_t> p_classes;
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// produce a fingerprint in p_classes
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int ninputs = module_inputs(m).size();
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std::vector<uint64_t> luts;
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if (!derive_module_luts(m, luts))
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continue;
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for (auto lut : luts)
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p_classes.insert(p_class(ninputs, lut));
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// save as a viable target
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targets[p_classes].push_back(Target{m, luts});
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}
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auto r = saved_designs.emplace("$cellmatch_map", nullptr);
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if (r.second)
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r.first->second = new Design;
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Design *map_design = r.first->second;
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for (auto m : d->selected_whole_modules_warn()) {
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std::vector<uint64_t> luts;
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if (!derive_module_luts(m, luts))
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continue;
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SigSpec inputs = module_inputs(m);
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SigSpec outputs = module_outputs(m);
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if (lut_attrs) {
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int no = 0;
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for (auto bit : outputs) {
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log_assert(bit.is_wire());
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bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
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bit.wire->attributes[ID(lut)] = luts[no++];
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}
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}
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// fingerprint
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pool<uint64_t> p_classes;
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for (auto lut : luts)
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p_classes.insert(p_class(inputs.size(), lut));
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for (auto target : targets[p_classes]) {
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log_debug("Candidate %s for matching to %s\n", log_id(target.module), log_id(m));
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SigSpec target_inputs = module_inputs(target.module);
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SigSpec target_outputs = module_outputs(target.module);
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if (target_inputs.size() != inputs.size())
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continue;
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if (target_outputs.size() != outputs.size())
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continue;
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std::vector<int> input_map;
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for (int i = 0; i < inputs.size(); i++)
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input_map.push_back(i);
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bool found_match = false;
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while (!found_match) {
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std::vector<int> output_map;
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for (int i = 0; i < outputs.size(); i++)
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output_map.push_back(i);
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while (!found_match) {
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int out_no = 0;
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bool match = true;
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for (auto lut : luts) {
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if (permute_lut(target.luts[output_map[out_no++]], input_map) != lut) {
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match = false;
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break;
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}
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}
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if (match) {
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log("Module %s matches %s\n", log_id(m), log_id(target.module));
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Module *map = map_design->addModule(stringf("\\_60_%s_%s", log_id(m), log_id(target.module)));
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Cell *cell = map->addCell(ID::_TECHMAP_REPLACE_, target.module->name);
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map->attributes[ID(techmap_celltype)] = m->name.str();
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for (int i = 0; i < outputs.size(); i++) {
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log_assert(outputs[i].is_wire());
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Wire *w = map->addWire(outputs[i].wire->name, 1);
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w->port_id = outputs[i].wire->port_id;
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w->port_output = true;
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log_assert(target_outputs[output_map[i]].is_wire());
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cell->setPort(target_outputs[output_map[i]].wire->name, w);
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}
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for (int i = 0; i < inputs.size(); i++) {
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log_assert(inputs[i].is_wire());
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Wire *w = map->addWire(inputs[i].wire->name, 1);
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w->port_id = inputs[i].wire->port_id;
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w->port_input = true;
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log_assert(target_inputs[input_map[i]].is_wire());
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cell->setPort(target_inputs[input_map[i]].wire->name, w);
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}
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map->fixup_ports();
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found_match = true;
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}
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if (!std::next_permutation(output_map.begin(), output_map.end()))
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break;
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}
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if (!std::next_permutation(input_map.begin(), input_map.end()))
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break;
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}
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}
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}
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}
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} CellmatchPass;
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YOSYS_NAMESPACE_END
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