mirror of https://github.com/YosysHQ/yosys.git
hierarchy: keep display statements, like formal assertions.
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2c4cf2b4b8
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3d9e44d182
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@ -655,6 +655,17 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
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log("Removed %d unused modules.\n", del_counter);
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}
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bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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{
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if (cache.count(mod) == 0)
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for (auto c : mod->cells()) {
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RTLIL::Module *m = mod->design->module(c->type);
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if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
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return cache[mod] = true;
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}
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return cache[mod];
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}
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bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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{
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if (cache.count(mod) == 0)
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@ -762,6 +773,11 @@ struct HierarchyPass : public Pass {
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log(" -nodefaults\n");
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log(" do not resolve input port default values\n");
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log("\n");
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log(" -nokeep_prints\n");
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log(" per default this pass sets the \"keep\" attribute on all modules\n");
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log(" that directly or indirectly display text on the terminal.\n");
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log(" This option disables this behavior.\n");
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log("\n");
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log(" -nokeep_asserts\n");
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log(" per default this pass sets the \"keep\" attribute on all modules\n");
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log(" that directly or indirectly contain one or more formal properties.\n");
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@ -818,6 +834,7 @@ struct HierarchyPass : public Pass {
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bool keep_positionals = false;
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bool keep_portwidths = false;
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bool nodefaults = false;
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bool nokeep_prints = false;
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bool nokeep_asserts = false;
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std::vector<std::string> generate_cells;
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std::vector<generate_port_decl_t> generate_ports;
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@ -893,6 +910,10 @@ struct HierarchyPass : public Pass {
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nodefaults = true;
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continue;
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}
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if (args[argidx] == "-nokeep_prints") {
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nokeep_prints = true;
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continue;
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}
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if (args[argidx] == "-nokeep_asserts") {
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nokeep_asserts = true;
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continue;
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@ -1091,6 +1112,15 @@ struct HierarchyPass : public Pass {
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}
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}
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if (!nokeep_prints) {
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std::map<RTLIL::Module*, bool> cache;
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for (auto mod : design->modules())
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if (set_keep_print(cache, mod)) {
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log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", log_id(mod));
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mod->set_bool_attribute(ID::keep);
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}
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}
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if (!nokeep_asserts) {
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std::map<RTLIL::Module*, bool> cache;
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for (auto mod : design->modules())
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