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Merge pull request #4333 from YosysHQ/fix_hierarchy_generate 

fix hierarchy -generate mode handling of cells
This commit is contained in:
N. Engelhardt 2024-04-25 09:56:24 +02:00 committed by GitHub
parent c3ae33da33 e8ec19c273
commit 34d9a7451e
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2 changed files with 21 additions and 1 deletions
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2
passes/hierarchy/hierarchy.cc
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@ -47,7 +47,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
{
if (design->module(cell->type) != nullptr)
continue;
if (cell->type.begins_with("$__"))
if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
continue;
for (auto &pattern : celltypes)
if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))

20
tests/various/hierarchy_generate.ys Normal file
View File

@ -0,0 +1,20 @@
read_verilog -icells <<EOF
module top(input [2:0] a, input [2:0] b, output [2:0] y);
sub sub_i (.a(a[0]), .b(b[0]), .y(y[0]));
unknown_sub sub_ii (.a(a[1]), .b(b[1]), .y(y[1]));
$__dunder_sub sub_iii (.a(a[2]), .b(b[2]), .y(y[2]));
endmodule
module sub(input a, input b, output y);
assign y = a ^ b;
endmodule
EOF
hierarchy -generate unknown_sub i:a i:b o:y
hierarchy -generate $__dunder_sub i:a i:b o:y
hierarchy -generate $xor i:A i:B o:Y # this one is ignored
hierarchy -top top -check
check -assert