mirror of https://github.com/YosysHQ/yosys.git
techmap: Support dynamic cell types
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@ -222,6 +222,8 @@ X(_TECHMAP_REPLACE_)
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X(techmap_simplemap)
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X(_techmap_special_)
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X(techmap_wrap)
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X(_TECHMAP_PLACEHOLDER_)
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X(techmap_chtype)
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X(T_FALL_MAX)
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X(T_FALL_MIN)
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X(T_FALL_TYP)
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@ -336,6 +336,9 @@ struct TechmapWorker
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if (c->type.begins_with("\\$"))
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c->type = c->type.substr(1);
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if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype))
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c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
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vector<IdString> autopurge_ports;
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@ -1135,6 +1138,10 @@ struct TechmapPass : public Pass {
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log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
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log("prefix also substituted.\n");
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log("\n");
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log("A cell with the type _TECHMAP_PLACEHOLDER_ in the map file will have its type\n");
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log("changed to the content of the techmap_chtype attribute. This allows for choosing\n");
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log("the cell type dynamically.\n");
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log("\n");
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log("See 'help extract' for a pass that does the opposite thing.\n");
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log("\n");
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log("See 'help flatten' for a pass that does flatten the design (which is\n");
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