mirror of https://github.com/YosysHQ/yosys.git
celledges: Register async FF paths
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87e72ef86f
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@ -360,6 +360,34 @@ void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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log_abort();
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}
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void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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int width = cell->getPort(ID::Q).size();
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if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
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for (int k = 0; k < width; k++) {
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db->add_edge(cell, ID::D, k, ID::Q, k, -1);
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db->add_edge(cell, ID::EN, 0, ID::Q, k, -1);
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}
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}
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if (cell->hasPort(ID::CLR))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::CLR, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::SET))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::SET, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::ALOAD))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ALOAD, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::AD))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::AD, k, ID::Q, k, -1);
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if (cell->hasPort(ID::ARST))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ARST, 0, ID::Q, k, -1);
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}
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PRIVATE_NAMESPACE_END
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bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
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@ -419,6 +447,13 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
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return true;
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}
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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ff_op(this, cell);
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return true;
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}
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// FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
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// FIXME: $lut $sop $alu $lcu $macc $fa
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// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
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// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux
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@ -224,7 +224,8 @@ struct CheckPass : public Pass {
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}
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}
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if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)))
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if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
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|| RTLIL::builtin_ff_cell_types().count(cell->type))
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edges_db.add_edges_from_cell(cell);
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}
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