mirror of https://github.com/YosysHQ/yosys.git
synthprop: Reformat the help
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118b2829db
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@ -185,35 +185,25 @@ struct SyntProperties : public Pass {
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log("\n");
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log(" synthprop [options]\n");
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log("\n");
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log("This creates synthesizable properties for selected module.\n");
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log("This creates synthesizable properties for the selected module.\n");
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log("\n");
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log("\n");
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log(" -name <portname>\n");
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log("\n");
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log("Name output port for assertions (default: assertions).\n");
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log("\n");
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log(" name of the output port for assertions (default: assertions).\n");
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log("\n");
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log(" -map <filename>\n");
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log("\n");
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log("Write port mapping for synthesizable properties.\n");
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log("\n");
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log(" write the port mapping for synthesizable properties into the given file.\n");
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log("\n");
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log(" -or_outputs\n");
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log("\n");
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log("Or all outputs together to create a single output that goes high when any\n");
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log("property is violated, instead of generating individual output bits.\n");
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log("\n");
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log(" Or all outputs together to create a single output that goes high when\n");
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log(" any property is violated, instead of generating individual output bits.\n");
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log("\n");
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log(" -reset <portname>\n");
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log("\n");
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log("Name of top-level reset input. Latch a high state on the generated outputs\n");
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log("until an asynchronous top-level reset input is activated.\n");
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log("\n");
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log(" name of the top-level reset input. Latch a high state on the generated\n");
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log(" outputs until an asynchronous top-level reset input is activated.\n");
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log("\n");
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log(" -resetn <portname>\n");
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log("\n");
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log("Name of top-level reset input (inverse polarity). Latch a high state on the\n");
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log("generated outputs until an asynchronous top-level reset input is activated.\n");
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log(" like above but with inverse polarity\n");
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log("\n");
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log("\n");
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}
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