same file), errors (buffer output pin name, power supplies not
passed at the top level). Corrected a major error that prevented
the use of the buffers in simulation, so this was not previously
verified by simulation. The buffering has now been properly
verified.
gpio_signal_buffering (gpio_signal_buffering_alt in caravan).
Note that this macro requires manual placement and routing, like
the padframe, and the top level will need to route around its own
internal routes.
- remove unused port in chip_io
- move the rest of chip_io power ports to the USE_POWER_PINS guard
- add caravel_power_routing cell guarded by TOP_ROUTING ifdef
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds
!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
* Effectively reverted the change to add spare logic blocks near each
of the GPIO control blocks by changing the definition of
NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks)
for both caravel and caravan top level RTL verilog modules.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Added enough spare logic blocks to have the existing four above
the processor, plus one each per GPIO (38 for caravel, 27 for
caravan).
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
* Removed the SRAM read-only interface by wrapping all related code
in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
to caravel_netlists.v when attempting to determine if the
verification testbenches could be run from caravel referencing
caravel_mgmt_soc_litex instead of the other way around. This file
has been reverted back to its original form.
This reverts commit 577cc12fe0.
Reverting the change from issue #16. After some discussion, it has
been decided that it is up to the user to implement the pull-up and
pull-down modes correctly by setting the output enable and driving
the output to the appropriate value. Note that this should be well
documented, if by nothing else than a validation testbench that
excercises a user pull-up and pull-down input mode.
kareem
mo-hosni
Marwan Abbas
Marwan Abbas
passant5
Passant
Tim Edwards
M0stafaRady
Mohamed Shalan
M0stafaRady
Jeff DiCorpo