fix power pins assignment of clockp buffers again

2022-10-13 11:02:35 -07:00 · 2022-10-13 11:02:35 -07:00 · d5379ab6f9
parent 633a204cdc
commit d5379ab6f9
1 changed files with 1 additions and 1 deletions
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@ -76,7 +76,7 @@ module digital_pll(
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPWR),
-        .VNB(vssd),
+        .VNB(VGND),
 `endif
        .A(clockp_buffer_in[0]),
        .X(clockp[0])