From d5379ab6f903b1f7f034f2e3ff9e20d9ccbe9b0b Mon Sep 17 00:00:00 2001 From: kareem Date: Thu, 13 Oct 2022 11:02:35 -0700 Subject: [PATCH] fix power pins assignment of clockp buffers again --- verilog/rtl/digital_pll.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v index 642406c3..a0dcb099 100644 --- a/verilog/rtl/digital_pll.v +++ b/verilog/rtl/digital_pll.v @@ -76,7 +76,7 @@ module digital_pll( .VPWR(VPWR), .VGND(VGND), .VPB(VPWR), - .VNB(vssd), + .VNB(VGND), `endif .A(clockp_buffer_in[0]), .X(clockp[0])